Signal processing algorithms represented by data flow graphs can be efficiently mapped to hardware using a block level pipelining architecture. In this scheme, nodes of data flow are mapped to processing blocks and bu...
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Signal processing algorithms represented by data flow graphs can be efficiently mapped to hardware using a block level pipelining architecture. In this scheme, nodes of data flow are mapped to processing blocks and buffers are inserted in between as pipelining elements. We present, in this paper, a methodology for equalizing execution times of various nodes in the data path. The method is used to minimize the power dissipation and buffer usage by judiciously selecting the execution speed of hardware units. The block level pipelining allows for simple local controllers for each buffer which are generated by the global controller based on data flow specifications. The evaluation of the methodology on a practical example is presented.
作者：
I. AndreadisA. AmanatiadisLaboratory of Electronics
Section of Electronics and Information Systems Technology Department of Electrical and Computer Engineering Democritus University of Thrace Xanthi Greece
The proposed scaling algorithm outperforms other standard and widely used scaling techniques. The algorithm uses a mask of maximum four pixels and calculates the final luminosity of each pixel combining two factors; t...
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The proposed scaling algorithm outperforms other standard and widely used scaling techniques. The algorithm uses a mask of maximum four pixels and calculates the final luminosity of each pixel combining two factors; the percentage of area that mask covers from each source pixel and the difference in luminosity between the source pixels. The interpolation is capable of scaling both grey-scale and color images of any resolution in any scaling factor. Its key characteristics and low complexity make the interpolation very fast and capable of real time implementation. The performance results in a variety of standard tests are presented and compared to other scaling algorithms
The paper explores a reconfigurable platform design methodology for high throughput execution of data centric applications. The reconfiguration platform consists of heterogenous processing elements and buffers interac...
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The paper explores a reconfigurable platform design methodology for high throughput execution of data centric applications. The reconfiguration platform consists of heterogenous processing elements and buffers interacting through reconfigurable interconnects. The proposed platform is based on block level pipelining with the buffers and their respective controllers forming the pipelining elements. We discuss the dynamic and partial reconfiguration techniques of this platform. Specifically, reconfiguration overhead at runtime is illustrated.
A custom simulation tool that combines HSPICE and MATLAB to enable time-domain noise analysis is reported. The simulation technique is based on computing the statistics of a random process by ensemble averaging and is...
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Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS time-interrupts, or static-com...
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Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS time-interrupts, or static-compiler techniques. However, substantially greater gains can be realized when control opportunities are also explored in a dynamic compilation environment. There are several advantages to deploying DVFS and managing energy/performance tradeoffs through the use of a dynamic compiler. Most importantly, dynamic compiler driven DVFS is fine-grained, code-aware, and adaptive to the current microarchitecture environment. This paper presents a design framework of the run-time DVFS optimizer in a general dynamic compilation system. A prototype of the DVFS optimizer is implemented and integrated into an industrial-strength dynamic compilation system. The obtained optimization system is deployed in a real hardware platform that directly measures CPU voltage and current for accurate power and energy readings. Experimental results, based on physical measurements for over 40 SPEC or Olden benchmarks, show that significant energy savings are achieved with little performance degradation. SPEC2K FP benchmarks benefit with energy savings of up to 70% (with 0.5% performance loss). In addition, SPEC2K INT show up to 44% energy savings (with 5% performance loss), SPEC95 FP save up to 64% (with 4.9% performance loss), and Olden save up to 61% (with 4.5% performance loss). On average, the technique leads to an energy delay product (EDP) improvement that is 3times-5times better than static voltage scaling, and is more than 2times (22% vs. 9%) better than the reported DVFS results of prior static compiler work. While the proposed technique is an effective method for microprocessor voltage and frequency control, the design framework and methodology described in this paper have broader potential to address other energy and power issues such as di/dt and thermal control
Enterprise integration is significant for the enforcement of novel business models in an enterprise/industry. The great heterogeneity of systems/applications in the enterprise environment requires the introduction of ...
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Enterprise integration is significant for the enforcement of novel business models in an enterprise/industry. The great heterogeneity of systems/applications in the enterprise environment requires the introduction of interoperability aspects in order to resolve integration problems in a flexible and dynamic way. Our approach introduces an advanced enterprise semantic model representing both enterprise structure and available services, through the use of ontologies. The model is associated by a specific architecture that uses the above model in combination with state-of-the-art technologies such as Web services and workflows
This paper presents a review of circuit design techniques related to silicon on insulator technology (SOI) CMOS circuits. The most important design considerations are parasitic bipolar effect, floating body effect and...
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This paper presents a review of circuit design techniques related to silicon on insulator technology (SOI) CMOS circuits. The most important design considerations are parasitic bipolar effect, floating body effect and hysteric variation in the threshold voltage. These effects lead to the reduction of the noise margin and under serious circumstances may lead to a wrong output. Dynamic circuits are most vulnerable to these effects due to the presence of a soft node at the top of the pull down stack. We have studied the various existing techniques and have proposed a design modification which alleviates the floating body effect without compromising other parameters like speed and without penalizing the charge sharing present. The approach is based on adding an extra transistor which will minimize the floating body effect without worsening charge sharing. The effectiveness of our design technique is demonstrated through its implementation in a 32-bit ANT logic carry look ahead adder using BSIMSOI models. Results show that the performance of the modified circuit is reliable and minimizes the floating body effect without adversely affecting charge sharing
Interconnect lengths have become a dominant factor in the design of integrated circuits. The parasitics associated with the interconnects account for a significant part of signal delay. The estimation of interconnect ...
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Interconnect lengths have become a dominant factor in the design of integrated circuits. The parasitics associated with the interconnects account for a significant part of signal delay. The estimation of interconnect lengths prior to placement helps in determining the delay early in the design phase. In this paper, a methodology to estimate the interconnect lengths prior to layout, is presented. The approach is heuristics based. Various layouts have been studied to observe typical placement and routing patterns. The methodology uses the gate level netlist and properties of the cells obtained from the standard cell libraries for the estimation. The results have been compared with the detailed routing wire lengths obtained after synthesis of the gate level netlist. Cadence Buildgates was used for syntheises and Cadence Encounter used for placement and routing of the circuits. The methodology presented is independent of the technology being used. However the wire lengths will vary with the use of different placement and routing tools
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