This paper presents a new technique for automatically creating analog circuit models. The method extracts piecewise linear models from trained neural networks. A model is a set of linear dependencies between circuit p...
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This paper presents a new technique for automatically creating analog circuit models. The method extracts piecewise linear models from trained neural networks. A model is a set of linear dependencies between circuit performances and design parameters. The paper illustrates the technique for an OTA circuit - an amplifier circuit widely used in filters and A/D converters for which models for gain and bandwidth were automatically generated. As experiments show, the obtained models have simple form that accurately fits the sampled points and the behavior of the trained neural networks. These models are useful for fast simulation of systems with non-linear behavior and performances.
Giving the ability to read characters and symbols is highly desirable for increased autonomy of mobile robots operating in the real world. The idea is fairly simple: give a robot the ability to acquire an image of a m...
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Giving the ability to read characters and symbols is highly desirable for increased autonomy of mobile robots operating in the real world. The idea is fairly simple: give a robot the ability to acquire an image of a message to read, extract the symbols and recognize them. Image character recognition research has been going on for decades now, with good results. But compared to conventional character recognition systems, the challenge with a mobile robot is to find a textual message to capture in the world and to get a good view of the message, knowing that the viewpoint of the robot depends on its position in relation to the message, which cannot be pre-specified. In this paper we present our approach making it possible for an autonomous mobile robot to read messages. We outline the constraints under which the approach works, and present results obtained using a Pioneer 2 robot equipped with a Pentium 233 MHz and a pan-tilt-zoom camera.
We present a paradigm which prescribes a procedure for a systematic design, analysis and development of nanopositioning devices. In this effort, we have used many tools from modern control theory to model devices, to ...
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We present a paradigm which prescribes a procedure for a systematic design, analysis and development of nanopositioning devices. In this effort, we have used many tools from modern control theory to model devices, to quantify device resolution, bandwidth, range, and robustness, and to tackle undesirable nonlinear effects such as hysteresis and creep. The implementation of this procedure for the simultaneous achievement of robustness, high precision, and high bandwidth objectives is presented. Emphasis is placed on the robustness aspects that make the nanopositioner operable in diverse need for tuning that is present paradigm are demonstrated operating conditions thus alleviating the need for tuning that is present in existing designs. The merits of the through experimental results.
Simultaneous multithreading (SMT) attempts to attain higher processor utilization by allowing instructions from multiple independent threads to coexist in a processor and compete for shared resources. Previous studies...
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Simultaneous multithreading (SMT) attempts to attain higher processor utilization by allowing instructions from multiple independent threads to coexist in a processor and compete for shared resources. Previous studies have shown, however, that its throughput may be limited by the number of threads. A reason is that a fixed thread scheduling policy cannot be optimal for the varying mixes of threads it may face in an SMT processor. Our adaptive dynamic thread scheduling (ADTS) was previously proposed to achieve higher utilization by allowing a detector thread to make use of wasted pipeline slots with nominal hardware and software costs. The detector thread adaptively switches between various fetch policies. Our previous study showed that a single fixed thread scheduling policy presents much room (some 30%) for improvement compared to an oracle-scheduled case. In this paper, we take a closer look at ADTS. We implemented the functional model of the ADTS and its software architecture to evaluate various heuristics for determining a better fetch policy for a next scheduling quantum. We report that performance could be improved by as much as 25%.
The pervasive computing environment and the wired grid infrastructure can be combined to make the information grid truly pervasive. Interesting applications can be built by utilizing the computational abilities of the...
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ISBN:
(纸本)9780769520261
The pervasive computing environment and the wired grid infrastructure can be combined to make the information grid truly pervasive. Interesting applications can be built by utilizing the computational abilities of the grid to answer queries on sensor data. We identify some of the research issues and challenges in building an infrastructure to support such applications. We present the design and preliminary implementation of the proposed infrastructure, identify the tradeoffs relating to sensor accuracy consumption, and report experimental results from a sample scenario involving firefighting.
This paper considers detection techniques for unresolved Ricean/Rayleigh fading multipath channels. It is well known that the optimal receiver has an estimator-correlator form, with a minimum mean-square error (MMSE) ...
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This paper considers detection techniques for unresolved Ricean/Rayleigh fading multipath channels. It is well known that the optimal receiver has an estimator-correlator form, with a minimum mean-square error (MMSE) estimate. With known multipath delays and unknown specular phases, the Ricean non-coherent multipath channel is a case where the received noiseless signal process is non-Gaussian, and the MMSE estimator is non-linear in the observation. This work presents novel, explicit expressions for such a MMSE estimator. It is shown that the MMSE estimate has the same multipath format as the noiseless received signal, with the unknown parameters replaced by corresponding estimates. The MMSE estimator scales down contributions from specular multipath components with poor phase estimates, reducing their effect on the detection process. The estimator includes a multipath decorrelation operation which is essential to avoid error floors over unresolved multipath channels. Based on matched filter bounds, it is shown that little degradation gains are obtained by employing suboptimal linear estimator-correlators, provided that they include the decorrelation operation.
This article presents the identification and control of a nano-positioning device. The device consists of two stages, which enable two-dimensional positioning. Each stage is actuated by piezo-electric stacks and its m...
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This article presents the identification and control of a nano-positioning device. The device consists of two stages, which enable two-dimensional positioning. Each stage is actuated by piezo-electric stacks and its motion is sensed by a linear variable differential transformer (LVDT). A 2 /spl times/ 2 transfer function has been identified to describe the device. In this paper the main limitations to nano-positioning have been overcome through control. Feedback laws have been designed to address the undesirable effects of hysteresis and creep, which are significant in the open loop implementation, and to meet the steady state tracking and bandwidth requirements of nano-positioning. Great emphasis has been placed on robustness, which leads to a system that can withstand the diverse conditions where it will be used and does not necessitate tuning, as is the case with the existing designs. Accordingly, Glover-McFarlane H/sub /spl infin// loop shaping controllers have been employed to robustify existing non-model based designs. The merits of these designs along with the experimental results obtained by using them have been presented.
This paper presents an application specific reconfigurable architecture based on coarse-grain FPGA for real-time parallel particle filters. The architecture consists of a set of heterogeneous arithmetic units and buff...
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This paper presents an application specific reconfigurable architecture based on coarse-grain FPGA for real-time parallel particle filters. The architecture consists of a set of heterogeneous arithmetic units and buffer banks, where their interconnections are reconfigurable at the hardware level. The proposed architecture separates fixed and reconfigurable units for high-throughput realization. We compare potential throughput of the design with that of commercial FPGAs and DSPs. The proposed architecture is implemented in 0.25 /spl mu/m CMOS process.
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