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VLab: An environment for teaching behavioral modeling 5th

引用

5th International Conference on Intelligent Tutoring systems, ITS 2000

作者： Tzafestas, Elpida S. Prokopiou, Platon A. Institute for Communication and Computer Systems Electrical and Computer Engineering Department National Technical University of Athens Zographou Campus Athens15773 Greece Digital Art Laboratory Athens School of Fine Arts Peiraios 256 Agios Ioannis Rentis18233 Greece

ISBN: (纸本)3540676554

Within the framework of a master in digital art, we have developed a set of educational tools for artificial life and the complexity sciences. These software tools constitute a laboratory curriculum that is used to supplement the theoretical courses on the subject and contain, among other things, an educational tool for behavioral modeling (VLab).

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A stand-alone integrated excitation/extraction system for analog BIST applications

A stand-alone integrated excitation/extraction system for an...

引用

Custom Integrated Circuits Conference (CICC)

作者： M.M. Hafed G.W. Roberts Microelectronics and Computer Systems Laboratory Department of Electrical and Computer Engineering McGill University Montreal QUE Canada

An integrated test core for mixed-signal circuits is described. The core consists of a completely digital implementation, except for a simple reconstruction filter and a comparator. It is capable of both generating arbitrary band-limited waveforms (for excitation purposes) and coherently digitizing arbitrary periodic analog waveforms (for DSP-based test and measurement). A prototype IC was fabricated in a 0.35 /spl mu/m CMOS process and was demonstrated to perform various curve tracing, oscilloscope, and spectrum analysis tasks.

关键词： Built-in self-test Circuit testing Signal generators Application software Hardware Band pass filters Microelectronics Laboratories System testing Digital filters

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A robust deep submicron programmable DC voltage generator

A robust deep submicron programmable DC voltage generator

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： M.M. Hafed S. Laberge G.W. Roberts Microelectronics and Computer Systems Laboratory Department of Electrical and Computer Engineering McGill University Montreal QUE Canada

An efficient technique for generating accurate on-chip DC reference voltages is presented. The technique is based on filtering a digital pulse-modulated sequence in order to extract its average (DC) value. Simplicity is achieved by using a passive on-chip filter and by using an all-digital implementation of the modulator. Moreover, in addition to using pulse-width modulation to encode the value of the output DC level, we propose the use of pulse-density modulation as a more viable technique. The latter has the advantage of using a significantly smaller filter, which translates into a smaller implementation area and a faster settling time. The technique was successfully demonstrated using a prototype IC in a 0.35 /spl mu/m CMOS process.

关键词： Robustness Voltage DC generators Pulse modulation Digital filters Filtering Passive filters Space vector pulse width modulation Prototypes CMOS integrated circuits

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An asynchronous FIFO with fights: case study in speed optimization

An asynchronous FIFO with fights: case study in speed optimi...

引用

IEEE International Conference on Electronics, Circuits and systems (ICECS)

作者： S. Laberge R. Negulescu Microelectronics and Computer Systems Laboratory Department of Electrical and Computer Engineering McGill University Montreal QUE Canada

ISBN: (纸本)0780365429

This paper describes an experiment in optimizing digital integrated circuits to maximize operating speeds. The circuit in question is an asynchronous FIFO originally designed for ultra-high-speed. To obtain an even higher throughput, we consider optimizations and local changes of the circuits by using fights, relative delay constraints, and asymmetric and skewed gates. We propose a transistor sizing procedure applicable in these conditions. Part of our procedure is based on the principles of logical effort; in addition, we investigate how to size the circuit with fights. The resulting circuit implemented in TSMC's 0.35 /spl mu/m technology can yield throughputs over 1500 millions items per second.

关键词： computer aided software engineering Delay Throughput Logic circuits Capacitance Equations Microelectronics Laboratories Digital integrated circuits Constraint optimization

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Interconnects for a multi-layer three-dimensional silicon architecture

Interconnects for a multi-layer three-dimensional silicon ar...

引用

2000 30th European Microwave Conference, EuMC 2000

作者： Herrick, Katherine J. Kihm, Robert T. Katehi, Linda P. B. Radiation Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI 49109-2122 United States Raytheon Systems Company El Segundo CA 90245 United States

As low cost and low volume gain increasing importance in today's technology market, the development of a silicon micro-machined multi-layer transmit module has become a worthwhile endeavor. In this architecture, the MMICs are flip-chip bonded and the 94 GHz signal is distributed both laterally and vertically through three silicon layers resulting in excitation of a four by four array of patch antennas. This module is 6 mm in length, 6 mm in width, 1 mm in height, and represents the first W-band transmit module to date. The details of the passive components and interconnects will be presented in this paper. © 2000 IEEE.

关键词： Silicon

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A rail-to-rail, constant-G/sub m/, 1-volt CMOS opamp

A rail-to-rail, constant-G/sub m/, 1-volt CMOS opamp

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： F. Bahmani S.M. Fakhraie A. Khakifirooz Electrical and Computer Engineering Department VLSI Circuits and Systems Laboratory University of Tehran Iran

A rail-to-rail, constant-g/sub m/, 1-volt only, full-CMOS opamp is presented. The opamp has a complementary PMOS/bulk-driven input stage with a feedback circuit to equalize g/sub m/, and a class AB output stage, which provide input and output rail-to-rail operation. HSPICE simulations are performed using BSIM 3.3 models of a 0.8 /spl mu/m CMOS process. This opamp has a DC gain of 45.1 dB, unity-gain bandwidth of 1.7 MHz, and phase margin of 63.4/spl deg/.

关键词： Feedback circuits Semiconductor device modeling MOSFETs Rail to rail operation Analog circuits Threshold voltage Very large scale integration Circuit simulation CMOS process Bandwidth

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parallel square and cube computations

Parallel square and cube computations

引用

Asilomar Conference on Signals, systems & computers

作者： A.A. Liddicoat M.J. Flynn Computer Systems Laboratory Department of Electrical Engineering University of Stanford Stanford CA USA

ISBN: (纸本)0780365143

Typically multipliers are used to compute the square and cube of an operand. A squaring unit can be used to compute the square of an operand faster and more efficiently than a multiplier This paper proposes a parallel cubing unit that computes the cube of an operand 25 to 30% faster than can be computed using multipliers. Furthermore, the reduced squaring and cubing units are mathematically modeled and the performance and area requirements are studied for operands up to 54 bits in length. The applicability of the proposed cubing circuit is discussed with relation to the current Newton-Raphson and Taylor series function evaluation units.

关键词： Concurrent computing Function approximation Taylor series Delay Circuits Table lookup Laboratories Newton method Indium tin oxide

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An efficient algorithm for the physical mapping of clustered task graphs onto multiprocessor architectures

An efficient algorithm for the physical mapping of clustered...

引用

Euromicro Workshop on parallel and Distributed Processing

作者： N. Koziris M. Romesis P. Tsanakas G. Papakonstantinou Department of Electrical and Computer Engineering Computer Science Division Computing Systems Laboratory National and Technical University of Athens Zografou Greece

The most important issue in sequential program parallelisation is the efficient assignment of computations into different processing elements. In the past, too many approaches were devoted in efficient program parallelization considering various models for the parallel programs and the target architectures. The most widely used parallelism description model is the task graph model with precedence constraints. Nevertheless, as far as physical mapping of tasks onto parallel architectures is concerned little research has given practical results. It is well known that the physical mapping problem is NP-hard in the strong sense, thus allowing only for heuristic approaches. Most researchers or tool programmers use exhaustive algorithms, or the classical method of simulated annealing. This paper presents an alternative approach onto the mapping problem. Given the graph of clustered tasks, and the graph of the target distributed architecture, our heuristic finds a mapping by first placing the highly communicative tasks on adjacent nodes of the processor network. Once these "backbone" tasks are mapped there is no backtracking, thus achieving low complexity. Therefore, the remaining tasks are placed beginning from those close to the "backbone" tasks. The paper concludes with performance and comparison results which reveal the method's efficiency.

关键词： Clustering algorithms Processor scheduling Network topology computer networks Application software Costs computer architecture computer science Laboratories Electronic mail

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Kalman-filtering timing recovery scheme for orthogonal frequency domain multiplexing (OFDM) systems

Kalman-filtering timing recovery scheme for orthogonal frequ...

引用

International Conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： M. Hajirostam M.A. Maddah-Ali A. Haft-Baradaran M.T. Kilani S.M. Fakhraie M. Sharif-Khani O. Shoaei VLSI Circuits and Systems Laboratory Department of Electrical and Computer Engineering University of Tehran Tehran Iran

This paper describes a new technique for timing synchronization in orthogonal frequency domain multiplexing (OFDM) transceiver systems. The proposed technique is based on non-synchronized sampling rate and no pilot is required to be transmitted. Therefore the transmission capacity is increased. The proposed algorithm employs the angles of the received symbols in the OFDM subchannels and provides a computationally efficient technique for estimation of the timing error. An equivalent state space model is also derived for timing error and then Kalman filtering method is exploited for tracking purposes. The proposed technique is very robust, particularly under low signal to noise ratio conditions and has been verified by means of computer simulations.

关键词： Timing OFDM computer errors Frequency synchronization Frequency domain analysis Transceivers Sampling methods State-space methods Kalman filters Filtering

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Fuzzy boundaries

Fuzzy boundaries

引用

International Conference on Information Technology Interfaces

作者： M.S. Stachowicz Laboratory for Intelligent Systems Electrical and Computer Engineering Department University of Minnesota Duluth MN USA

ISBN: (纸本)9539676916

The primary purpose of this lecture is to provide the participant with a comprehensive coverage of theoretical foundation of digital fuzzy set theory (DFS) and multivalued logic (MVL), as well as a broad overview of the increasingly important applications of these new areas of mathematics. Due to computational efficiency DFS and MVL could be used extensively, especially in real time implementations. Throughout the paper, many examples are used to illustrate concepts, methods, and genetic applications. The applications, which are multi-disciplinary in nature, include computing with words, automatic control, image processing, database management, pattern recognition and so on.

关键词： Fuzzy logic Fuzzy set theory Set theory Fuzzy systems Laboratories Intelligent systems Multivalued logic Mathematics Genetics Automatic control

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