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Controlled vs. Automatic Processing: A Graph-Theoretic Approach to the Analysis of Serial vs. parallel Processing in Neural Network Architectures 38

Controlled vs. Automatic Processing: A Graph-Theoretic Appro...

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38th Annual Meeting of the Cognitive Science Society: Recognizing and Representing Events, CogSci 2016

作者： Musslick, Sebastian Dey, Biswadip Özcimder, Kayhan Patwary, Md. Mostofa Ali Willke, Theodore L. Cohen, Jonathan D. Princeton Neuroscience Institute Princeton University PrincetonNJ08544 United States Department of Mechanical and Aerospace Engineering Princeton University PrincetonNJ08544 United States Parallel Computing Lab Intel Corporation Santa ClaraCA95054 United States

ISBN: (纸本)9780991196739

The limited ability to simultaneously perform multiple tasks is one of the most salient features of human performance and a defining characteristic of controlled processing. Based on the assumption that multitasking constraints arise from shared representations between individual tasks, we describe a graph-theoretic approach to analyze these constraints. Our results are consistent with previous numerical work (Feng, Schwemmer, Gershman, & Cohen, 2014), showing that even modest amounts of shared representation induce dramatic constraints on the parallel processing capability of a network architecture. We further illustrate how this analysis method can be applied to specific neural networks to efficiently characterize the full profile of their parallel processing capabilities. We present simulation results that validate theoretical predictions, and discuss how these methods can be applied to empirical studies of controlled vs. and automatic processing and multitasking performance in humans. © 2016 Proceedings of the 38th Annual Meeting of the Cognitive Science Society, CogSci 2016. All rights reserved.

关键词： Multitasking

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Real-time full correlation matrix analysis of fMRI data

Real-time full correlation matrix analysis of fMRI data

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IEEE International Conference on Big Data

作者： Yida Wang Bryn Keller Mihai Capota Michael J. Anderson Narayanan Sundaram Jonathan D. Cohen Kai Li Nicholas B. Turk-Browne Theodore L. Willke Parallel Computing Lab Intel Corporation Princeton Neuroscience Institute Princeton University Department of Computer Science Princeton University

ISBN: (纸本)9781467390064

Real-time functional magnetic resonance imaging (rtfMRI) is an emerging approach for studying the functioning of the human brain. Computational challenges combined with high data velocity have to this point restricted rtfMRI analyses to studying regions of the brain independently. However, given that neural processing is accomplished via functional interactions among brain regions, neuroscience could stand to benefit from rtfMRI analyses of full-brain interactions. In this paper, we extend such an offline analysis method, full correlation matrix analysis (FCMA), to enable its use in rtfMRI studies. Specifically, we introduce algorithms capable of processing real-time data for all stages of the FCMA machine learning workflow: incremental feature selection, model updating, and real-time classification. We also present an actor-model based distributed system designed to support FCMA and other rtfMRI analysis methods. Experiments show that our system successfully analyzes a stream of brain volumes and returns neurofeedback with less than 180 ms of lag. Our real-time FCMA implementation provides the same accuracy as an optimized offline FCMA toolbox while running 3.6-6.2× faster.

关键词： Big data Machine-to-machine communications Conferences

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Espresso: Brewing Java for More Non-Volatility with Non-volatile Memory

arXiv

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arXiv 2017年

作者： Wu, Mingyu Zhao, Ziming Li, Haoyu Li, Heting Chen, Haibo Zang, Binyu Guan, Haibing Shanghai Key Lab. of Scalable Computing and Systems Institute of Parallel and Distributed Systems Shanghai Jiao Tong University

Fast, byte-addressable non-volatile memory (NVM) em-braces both near-DRAM latency and disk-like persistence, which has generated considerable interests to revolutionize system software stack and programming models. However, it is less understood how NVM can be combined with managed runtime like Java virtual machine (JVM) to ease persistence management. This paper proposes Espresso1, a holistic ex-tension to Java and its runtime, to enable Java programmers to exploit NVM for persistence management with high perfor-mance. Espresso first provides a general persistent heap de-sign called Persistent Java Heap (PJH) to manage persistent data as normal Java objects. The heap is then strengthened with a recoverable mechanism to provide crash consistency for heap metadata. It then provides a new abstraction called Persistent Java Object (PJO) to provide an easy-to-use but safe persistent programming model for programmers to per-sist application data. The evaluation confirms that Espresso significantly outperforms state-of-art NVM support for Java (i.e., JPA and PCJ) while being compatible to existing data structures in Java programs. Copyright © 2017, The Authors. All rights reserved.

关键词： Nonvolatile storage

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A team algorithm for robust stability analysis and control design of uncertain time-varying linear systems using piecewise quadratic Lyapunov functions

A team algorithm for robust stability analysis and control d...

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IEEE Conference on Decision and Control

作者： H.L.S. Almeida A. Bhaya D.M. Falcao E. Kaszkurewicz Lab for Parallel Computing Federal University of Rio de Janeiro Rio de Janeiro Rio de Janeiro Brazil

We introduce the use of team algorithms using piecewise quadratic simultaneous Lyapunov functions for robust stability analysis and control design problems involving uncertain time-varying linear systems. The objective is to employ robust stability criteria that are less conservative than the well-known quadratic stability approach. The use of piecewise quadratic Lyapunov functions leads to a non-convex optimization problem, which is solved by a team algorithm that is a combination of a genetic algorithm with an interior-point method for linear matrix inequalities. Numerical examples are given, showing the advantages of the proposed solution.

关键词： Robust stability Algorithm design and analysis Control design Lyapunov method Control system analysis Time varying systems Linear systems Stability criteria Optimization methods Genetic algorithms

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Network Coding Scheme Behavior in a Vehicle-to-Vehicle Safety Message Dissemination

Network Coding Scheme Behavior in a Vehicle-to-Vehicle Safet...

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International Conference on Communications Workshops

作者： Imen Achour Tarek Bejaoui Anthony Busson Sami Tabbane Mediatron Lab. SupCom University of Carthage Tunisia Laboratory of Parallel Computing University of Lyon 1 - ENS - Inria France

ISBN: (纸本)9781509015269

Message dissemination is considered as a challenging task in Vehicular Ad-hoc network (VANET). In particular, safety messages, such as, road accident warning, traffic congestion warning, etc., are the most critical messages type that need to be efficiently transmitted in a wireless and mobile network where the topology changes dynamically. Many protocols have been proposed for the sake of disseminating information with a high data reachability and a low end-to-end delay in a limited bandwidth. In this work, we focus on a new trend of dissemination protocols based on the "Network Coding" (NC) scheme. Precisely, we intent to study the NC gain toward safety message dissemination and deduce its suitability in accordance to such application requirements. To this end, three NC-based protocols are proposed for the aim at thoroughly studying the impact of such technique on the safety message dissemination performance. The gain of NC scheme is studied under different traffic densities (from low to high dense network). The simulation results show that NC could be an efficient solution to overcome the intermittent connectivity in sparse network mainly for comfort applications but not suitable for safety message dissemination, especially in high dense network, since it may introduce a high transmission delay.

关键词： Vehicular Ad hoc Networks Network Coding Data Dissemination Vehicle-to-Vehicle Communication Intelligent Transportation System

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An efficient local address generation for the block-cyclic distribution 3

An efficient local address generation for the block-cyclic d...

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3rd International Conference on Algorithms and Architectures for parallel Processing, ICA3PP 1997

作者： Kwon, Oh-Young Kim, Tae-Geun Han, Tack-Don Yang, Sung-Bong Kim, Shin-Dug Distributed Computing Lab. Systems Engineering Research Institute 1 Ueun-dong Yusong-gu Taejon305-333 Korea Republic of Parallel Processing System Laboratory Dept. of Computer Science Yonsei University Seoul120-749 Korea Republic of

ISBN: (纸本)0780342291

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time ΔM table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a ΔM table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time ΔM table generation method is faster than other algorithms in ΔM table generation time and access time for 10,000 array elements. © 1997 IEEE.

关键词： Virtual addresses

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CLSIFT: An optimization study of the scale invariance feature transform on GPUs

CLSIFT: An optimization study of the scale invariance featur...

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15th IEEE International Conference on High Performance computing and Communications, HPCC 2013 and 11th IEEE/IFIP International Conference on Embedded and Ubiquitous computing, EUC 2013

作者： Wang, Weiyan Zhang, Yunquan Guoping, Long Yan, Shengen Jia, Haipeng Lab. of Parallel Software and Computational Science Institute of Software Chinese Academy of Sciences China State Key Laboratory of Computing Science Institute of Software Chinese Academy of Sciences China School of Computer and Control Engineering University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9780769550886

Scale Invariance Feature Transform (SIFT) is quite suitable for image matching because of its invariance to image scaling, rotation and slight changes in illumination or viewpoint. However, due to high computation complexity it's technically challenging to deploy SIFT in real time application situations. To address this problem, we propose CLSIFT, an OpenCL based highly speeded up and performance portable SIFT solution. Important optimization techniques employed in CLSIFT such as: (1) For less global memory traffic, independent logical functions are merged into the same kernel to reuse data.(2) loop buffers are introduced in for data and intermediate results reusing.(3)Task queue used to schedule threads in the same branch to remove branch divergences. (4) Data partition is based on the statics patterns for workload balance among workgroups. (5) Overlap of CPU time and better parallel strategies are used too. With all mentioned efforts, CLSIFT processes lena. jpg at 74.2 FPS and 43.4FPS respectively on NVidia and AMD GPUS, much higher than CPU's nearly 10 FPS and the known fastest SIFTGPU's 39.8 FPS and 13FPS. Moreover in a quantitative comparison approach we analyze those successful strategies beating SIFTGPU, a famous existing GPU implementation. Additionally, we observe and conclude that NVidia GPU achieves better occupancy and performance due to some factors. Finally, we summarize some techniques and empirical guiding principles that may be shared by other applications on GPU. © 2013 IEEE.

关键词： Graphics processing unit

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Versatile and scalable parallel histogram construction

Versatile and scalable parallel histogram construction

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International Conference on parallel Architecture and Compilation Techniques (PACT)

作者： Wookeun Jung Jongsoo Park Jaejin Lee Department of Computer Science and Engineering Seoul National University Seoul Korea Intel Corporation Parallel Computing Lab California USA

ISBN: (纸本)9781509066070

Histograms are used in various fields to quickly profile the distribution of a large amount of data. However, it is challenging to efficiently utilize abundant parallel resources in modern processors for histogram construction. To make matters worse, the most efficient implementation varies depending on input parameters (e.g., input distribution, number of bins, and data type) or architecture parameters (e.g., cache capacity and SIMD width). This paper presents versatile histogram methods that achiev competitive performance across a wide range of input types and target architectures. Our open source implementations are highly optimized for various cases and are scalable for more threads and wider SIMD units. We also show that histogram construction can be significantly accelerated by Intel ® Xeon Phi coprocessors for common input data sets because of their compute power from many cores and instructions for efficient vectorization, such as gather-scatter. For histograms with 256 fixed-width bins, a dual-socket 8-core Intel ® Xeon ® E5-2690 achieves 13 billion bin updates per second (GUPS), while a 60-core Intel ® Xeon Phi 5110P coprocessor achieves 18 GUPS for a skewed input. For histograms with 256 variable-width bins, the Xeon processor achieves 4.7 GUPS, while the Xeon Phi coprocessor achieves 9.7 GUPS for a skewed input. For text histogram, or word count, the Xeon processor achieves 342.4 million words per seconds (MWPS). This is 4.12×, 3.46× faster than PHOENIX and TBB. The Xeon phi processor achieves 401.4 MWPS, which is 1.17× faster than the Xeon processor. Since histogram construction captures essential characteristics of more general reduction-heavy operations, our approach can be extended to other settings.

关键词： Histograms Instruction sets Computer architecture Hardware parallel processing Coprocessors

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Practical massively parallel monte-carlo tree search applied to molecular design

arXiv

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arXiv 2020年

作者： Yang, Xiufeng Aasawat, Tanuj Kr Yoshizoe, Kazuki Chugai Pharmaceutical Co. Ltd Parallel Computing Lab - India Intel Labs RIKEN Center for Advanced Intelligence Project

It is common practice to use large computational resources to train neural networks, known from many examples, such as reinforcement learning applications. However, while massively parallel computing is often used for training models, it is rarely used to search solutions for combinatorial optimization problems. This paper proposes a novel massively parallel Monte-Carlo Tree Search (MP-MCTS) algorithm that works efficiently for a 1,000 worker scale on a distributed memory environment using multiple compute nodes and applies it to molecular design. This paper is the first work that applies distributed MCTS to a real-world and non-game problem. Existing works on large-scale parallel MCTS show efficient scalability in terms of the number of rollouts up to 100 workers. Still, they suffer from the degradation in the quality of the solutions. MP-MCTS maintains the search quality at a larger scale. By running MP-MCTS on 256 CPU cores for only 10 minutes, we obtained candidate molecules with similar scores to non-parallel MCTS running for 42 hours. Moreover, our results based on parallel MCTS (combined with a simple RNN model) significantly outperform existing state-of-the-art work. Our method is generic and is expected to speed up other applications of MCTS1 Copyright © 2020, The Authors. All rights reserved.

关键词： Trees (mathematics)

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parallel Mutual Information Based Construction of Whole-Genome Networks on the Intel (R) Xeon Phi (TM) Coprocessor

Parallel Mutual Information Based Construction of Whole-Geno...

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International Symposium on parallel and Distributed Processing (IPDPS)

作者： Sanchit Misra Kiran Pamnany Srinivas Aluru Parallel Computing Lab Intel Corporation Bangalore India School of Computational Science and Engineering Georgia Institute of Technology Atlanta USA

Construction of whole-genome networks from large-scale gene expression data is an important problem in systems biology. While several techniques have been developed, most cannot handle network reconstruction at the whole-genome scale, and the few that can, require large clusters. In this paper, we present a solution on the Intel (R) Xeon Phi (TM) coprocessor, taking advantage of its multi-level parallelism including many x86-based cores, multiple threads per core, and vector processing units. We also present a solution on the Intel (R) Xeon (R) processor. Our solution is based on TINGe, a fast parallel network reconstruction technique that uses mutual information and permutation testing for assessing statistical significance. We demonstrate the first ever inference of a plant whole genome regulatory network on a single chip by constructing a 15,575 gene network of the plant Arabidopsis thaliana from 3,137 microarray experiments in only 22 minutes. In addition, our optimization for parallelizing mutual information computation on the Intel Xeon Phi coprocessor holds out lessons that are applicable to other domains.

关键词： Vectors Joints Coprocessors Mutual information Optimization Splines (mathematics) Arrays

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