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International Conference on parallel Processing (ICPP)

作者： Subburajan Ponnuswamy Vipin Chaudhary Parallel and Distributed Computing Laboratory Department of ECE Wayne State University Detroit MI USA

Star graph is an extensively studied Cayley graph, considered to be an attractive alternative to the popular binary cube. The rotator graphs are a set of directed Cayley graphs introduced recently. In this paper we compare the structural and algorithmic aspects of star graphs with that of rotator graphs. In the process we present some new results for star graphs and rotator graphs. We present a formula for the number of nodes at any distance from the identity permutation in star graphs. The minimum bisection width of star and rotator graphs is obtained. Partitioning and fault tolerant parameters for both star and rotator graphs are analyzed. The node disjoint parallel paths and hence the upper bound on the fault diameter of rotator graphs are presented. We compare the minimal path routing in star and rotator graphs using simulation results.

关键词： Routing Fault tolerance Tin parallel processing distributed computing Laboratories Delay Computational modeling Upper bound Multiprocessing systems

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Embedding of cycles in rotator and incomplete rotator graphs

Embedding of cycles in rotator and incomplete rotator graphs

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International Symposium on parallel and distributed Processing (IPDPS)

作者： S. Ponnuswamy V. Chaudhary Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University Detroit MI USA

Symmetric directed Cayley graphs called rotator graphs have been proposed recently in the literature. In addition to a lower diameter and average distance compared to the star graph, hypercube, and k-ary n-cubes, these rotator graphs also have a rich cyclic structure. We identify a variety of disjoint cycles in rotator graphs. An efficient algorithm for Hamiltonian cycles in rotator graphs is presented. This algorithm uses a basic sequence of four generators repeatedly with generators of higher order in between, to obtain Hamiltonian cycle in any n-rotator graph. We study the embedding of undirected cycles and directed cycles in rotator graphs. We also prove that the incomplete rotator graph obtained from the rotator graph is Hamiltonian. The embedding of undirected rings in rotator graphs is shown to have a low average dilation.< >

关键词： Multiprocessor interconnection networks distributed computing parallel processing Algorithm design and analysis Laboratories Concurrent computing Hypercubes Optical fiber communication Very large scale integration Protocols

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Contention sensitive fault-tolerant routing algorithms for hypercubes

Contention sensitive fault-tolerant routing algorithms for h...

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International Symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： R. Srinivasan V. Chaudhary S.M. Mahmud Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University Detroit MI USA

We present two new fault tolerant routing algorithms for hypercubes. The first algorithm requires only local knowledge of the faults whereas the second algorithm requires global knowledge. Unlike previous fault tolerant routing algorithms, our algorithms take into consideration the dynamic conditions (link contention) of the network. We have shown that checking for dynamic conditions in fault tolerant algorithms is essential. Performance evaluation by extensive simulation of our algorithms and other fault tolerant routing algorithms show that ours are better than previous algorithms by as much as 50%; and 500%; in time and space, respectively. We also observed that global information about the location of faults does not give us additional benefit. This observation is true regardless of the consideration of the dynamic conditions in the network.< >

关键词： Fault tolerance Routing Hypercubes Telecommunication traffic distributed computing Laboratories Network topology Scalability Hardware Adaptive algorithm

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Minimum dependence distance tiling of nested loops with non-uniform dependences

Minimum dependence distance tiling of nested loops with non-...

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International Symposium on parallel and distributed Processing (IPDPS)

作者： S. Punyamurtula V. Chaudhary Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University Detroit MI USA Wayne State University

We address the problem of partitioning nested loops with non-uniform (irregular) dependence vectors. Although many methods exist for nested loop partitioning, most of these perform poorly when parallelizing nested loops with irregular dependencies. We apply the results of classical convex theory and principles of linear programming to iteration spaces and show the correspondence between minimum dependence distance computation and iteration space tiling. The cross-iteration dependencies are analyzed by forming an Integer Dependence Convex Hull (IDCH). A simple way to compute minimum dependence distances from the dependence distance vectors of the extreme points of the IDCH is presented. Using these minimum dependence distances the iteration space can be tiled. Iterations in a tile can be executed in parallel and the tiles can be executed with proper synchronization. We demonstrate that our technique gives much better speedup and extracts more parallelism than the existing techniques.< >

关键词： Tiles distributed computing Concurrent computing Vectors Linear programming parallel processing Laboratories Sequential analysis Data analysis Data mining

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MANIPULATIONS OF OCTREES AND QUADTREES ON MULTIPROCESSORS

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International Journal of Pattern Recognition and Artificial Intelligence 1994年第2期8卷 439-455页

作者： VIPIN CHAUDHARY K. KUMARI P. ARUNACHALAM J.K. AGGARWAL Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University Detroit MI 48202 USA Sun Microsystems 2820 Orchard Parkway San Jose CA 95134 USA Computer and Vision Research Center Department of Electrical and Computer Engineering University of Texas at Austin Austin Texas 78712–1084 USA

Octrees offer a powerful means for representing and manipulating 3-D objects. This paper presents an implementation of octree manipulations using a new approach on a shared memory architecture. Octrees are hierarchical data structures used to model 3-D objects. The manipulation of these data structures involves performing independent computations on each node of the octree. Octrees are much easier to deal with than other forms of representations used to model 3-D objects especially where extensive manipulations are involved. When these operations are distributed among multiple processing elements (PEs) and executed simultaneously, a significant speedup may be achieved. Manipulations such as a complement, a union, an intersection and other operations such as finding the volume and centroid which this paper describes are implemented on the Sequent Balance multiprocessor. In this approach the PEs are allocated dynamically, resulting in a uniform load balancing among them. The experimental results presented illustrate the feasibility of the approach. Although this evaluation has been originally done for shared memory machines, it will provide insight for the evaluation of other architectures.

关键词： Shared memory architecture dynamic allocation union intersection orthogonal views

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Mapping algorithms for permutation networks

Mapping algorithms for permutation networks

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： V. Chaudhary Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University Detroit MI USA

The mapping problem arises when the dependency structure of a parallel algorithm differs from the interconnection of processors in the intended parallel computer (topological variation) or, when the number of processes required by the algorithm exceeds the number of processors available in the computer (cardinality variation). The problem discussed in this paper is to identify a distributed computing environment that best optimizes the objective function for the given problem. Distinct network permutations may result in equivalent process permutation depending upon the mapping of processes onto the processors. In this paper we study the permuting properties of dynamic interconnection networks taking process mapping into consideration. A uniform group theoretic representation for interconnection networks is developed. Finally, an algorithm to evaluate the number of passes required by an interconnection network to realize a given mapping is presented.< >

关键词： Multiprocessor interconnection networks distributed computing Concurrent computing parallel algorithms Multiprocessing systems Laboratories Costs Delay effects Routing

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Embedding of meshes on rotator graphs

Embedding of meshes on rotator graphs

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： S. Ponnuswamy V. Chaudhary Dept. of Electr. & Comput. Eng. Wayne State Univ. Detroit MI USA Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University Detroit MI USA

A set of directed permutation graphs called rotator graphs were proposed as an alternative to the star and pancake graphs for multiprocessor interconnection networks. The rotator graphs have a smaller diameter than star and pancake graphs for the same number of nodes, while sharing the properties of star, pancake, and binary hypercubes like maximal fault tolerance, partitionability, etc. In this paper we develop a class of algorithms for recognizing undirected mesh structures in n-rotator graphs. The average dilation of the embeddings are very low as compared to the dilation of the embedding. These embeddings will be very useful for regular computations with bi-directional requirements, in addition to the irregular computations in n-rotator graphs. Most of the results presented here equally apply to another set of directed Cayley graphs, the cycle prefix digraphs.< >

关键词： Multiprocessor interconnection networks Hypercubes Bidirectional control Concurrent computing Fault tolerance Embedded computing Routing Application software Sorting Computer vision

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OMP: a RISC-based multiprocessor using orthogonal-access memories and multiple spanning buses 90

OMP: a RISC-based multiprocessor using orthogonal-access mem...

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Proceedings of the 4th international conference on Supercomputing

作者： K. Hwang M. Dubois D. K. Panda S. Rao S. Shang A. Uresin W. Mao H. Nair M. Lytwyn F. Hsieh J. Liu S. Mehrotra C. M. Cheng Laboratory for Parallel and Distributed Computing University of Southern California Los Angeles CA

ISBN: (纸本)9780897913690

This paper presents the architectural design and RISC based implementation of a prototype supercomputer, namely the Orthogonal MultiProcessor (OMP). The OMP system is constructed with 16 Intel 1860 RISC microprocessors and 256 parallel memory modules, which are 2-D interleaved and orthogonally accessed using custom-designed spanning buses. The architectural design has been validated by a CSIM-based multiprocessor simulator. The design choices are based on worst-case delay analysis and simulation validation. The current OMP prototype chooses a 2-dimensional memory architecture, mainly for image processing, computer vision, and neural network simulation applications. The 16-processor OMP prototype is targeted to achieve a peak performance of 400 RISC integer MIPS or a maximum of 640 Mflops. This paper presents the architectural design of the OMP prototype at system and PC board levels. We are presently entering the fabrication stage of all the PC boards. The system is expected to become operational in late 1991 and benchmarking results will be available in 1992. Only hardware design features are reported here. Software and simulation results are reported elsewhere.

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Grid and Cooperative computing - GCC 2004 Workshops 1

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丛书名： Lecture Notes in Computer Science

1000年

作者： Hai Jin Yi Pan Nong Xiao Jianhua Sun

ISBN: (数字)9783540302070

ISBN: (纸本)9783540235781

Welcome to the proceedings of GCC2004 and the city of Wuhan. Grid computing has become a mainstream research area in computer science and the GCC conference has become one of the premier forums for presentation of new and exciting research in all aspectsofgridandcooperativecomputing. Theprogramcommitteeispleasedtopresent the proceedings of the 3rd International Conference on Grid and Cooperative Comp- ing (GCC2004), which comprises a collection of excellent technical papers, posters, workshops, and keynote speeches. The papers accepted cover a wide range of exciting topics, including resource grid and service grid, information grid and knowledge grid, grid monitoring,managementand organizationtools, grid portal, grid service, Web s- vices and their QoS, service orchestration, grid middleware and toolkits, software glue technologies, grid security, innovative grid applications, advanced resource reservation andscheduling,performanceevaluationandmodeling,computer-supportedcooperative work, P2P computing, automatic computing, and meta-information management. The conference continues to grow and this year a record total of 581 manuscripts (including workshop submissions) were submitted for consideration. Expecting this growth, the size of the program committee was increased from 50 members for GCC 2003 for 70 in GCC 2004. Relevant differences from previous editions of the conf- ence: it is worth mentioning a signi?cant increase in the number of papers submitted by authors from outside China; and the acceptance rate was much lower than for p- vious GCC conferences. From the 427 papers submitted to the main conference, the program committee selected only 96 regular papers for oral presentation and 62 short papers for poster presentation in the program.

关键词： Theory of Computation Computer Communication Networks Operating Systems Information Systems Applications (incl. Internet) Information Storage and Retrieval User Interfaces and Human Computer Interaction

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SPDFA: A Novel Dataflow Fusion Sparse Deep Neural Network Accelerator

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ACM Transactions on Reconfigurable Technology and Systems 1000年

作者： Jinwei Xu Jingfei Jiang Lei Gao Xifu Qian Yong Dou National University of Defense Technology National Key Laboratory of Parallel and Distributed Computing China

Unstructured sparse pruning significantly reduces the computational and parametric complexities of deep neural network models. Nevertheless, the highly irregular nature of sparse models limits its performance and efficiency on traditional computing platforms, thereby prompting the development of specialized hardware solutions. To improve computational efficiency, we introduce the Sparse Dataflow Fusion Accelerator (SPDFA), a specialized architecture meticulously designed for sparse deep neural networks. Firstly, we present a non-blocking data distribution-computing engine that integrates inner product and column product. This engine boosts computational efficiency by decomposing matrix multiplication and convolution into rectangular matrix-vector multiplications. Secondly, we implement a computation array to further exploit the parallelism, and design an on-chip buffer structure that supports multi-line memory access mode. Lastly, to bolster the adaptability of our accelerator, we propose an innovative macroinstruction set coupled with a micro-kernel scheme. Furthermore, we refine the macroinstruction issue strategy, thereby further enhancing computational efficiency. Our evaluation results demonstrate that SPDFA achieves an average 1.29\(\times\)-2.38\(\times\) improvement in computational efficiency compared to the state-of-the-art SpMM accelerators when applied to unstructured sparse deep neural network models. Furthermore, its performance outperforms existing sparse neural network accelerators by a factor of 1.03\(\times\)-1.83\(\times\). Additionally, SPDFA exhibits excellent scalability with a scaling efficiency exceeding 80%.

关键词： Unstructured Sparse Dataflow Fusion computing Unit Multi-line Memory Access Mode

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