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IEEE International Conference on Computer and Communications, ICCC 2015

作者： Zhou, Tong Guo, Song Lei, Yuanwu Dou, Yong National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781467381253

This paper aimed to improve MIMO detector's performance in both throughput and cost. Thus, it presents a FPGA architecture implementation for the SQRD detection in a 4 × 4 16-QAM MIMO wireless communication systems. The exploitation of fine-grained parallelism and coarse-grained parallelism strategies are responsible for bettering the performance of the implementation. Besides, this paper proposes a method to ensure the correctness of the implementation of time-sharing modules, which is general and applicable to any MIMO detector implementation. The work results in a real-time FPGA-based implementation delivering 32 MSQRD/s with 5.2 us latency and lowering more than 50\% cost in hardware resources on a Xilinx Virtex6. © 2015 IEEE.

关键词： Field programmable gate arrays (FPGA)

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GPU acceleration of subgraph isomorphism search in large scale graph

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Journal of Central South University 2015年第6期22卷 2238-2249页

作者：杨博卢凯高颖慧王小平徐凯 Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology College of Computer National University of Defense Technology Department of Electronic Science and Engineering National University of Defense Technology

A novel framework for parallel subgraph isomorphism on GPUs is proposed, named GPUSI, which consists of GPU region exploration and GPU subgraph matching. The GPUSI iteratively enumerates subgraph instances and solves the subgraph isomorphism in a divide-and-conquer fashion. The framework completely relies on the graph traversal, and avoids the explicit join operation. Moreover, in order to improve its performance, a task-queue based method and the virtual-CSR graph structure are used to balance the workload among warps, and warp-centric programming model is used to balance the workload among threads in a warp. The prototype of GPUSI is implemented, and comprehensive experiments of various graph isomorphism operations are carried on diverse large graphs. The experiments clearly demonstrate that GPUSI has good scalability and can achieve speed-up of 1.4–2.6 compared to the state-of-the-art solutions.

关键词： parallel graph isomorphism GPU backtrack paradigm

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Benchmarking the Powering Computations for Application Tuning

Benchmarking the Powering Computations for Application Tunin...

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International Conference on Software Analysis, Testing and Evolution (SATE)

作者： Yongang Che Chuanfu Xu Zhenghua Wang Computer College National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory (PDL) National University of Defense Technology Changsha China

ISBN: (纸本)9781509045181

Powering is an important operation in many computation intensive workloads. This paper investigates the performance of different styles to calculate the powering operations from the application level. A series of small benchmark codes that calculate the powering operations in different ways are designed. Their performance is evaluated on Intel Xeon CPU under Intel compilation environments. The results show that the number of floating-point operations and the related runtime are sensitive to the value of the exponent Y and how it is used. When Y is an immediate integer number whose value is known at compile time, the cost of powering is much less than the situation when Y is an integer variable whose value is known at runtime. When Y is defined as a real variable, the cost of powering is always high, be it equals to an integer number or not. Based on the investigations, performance optimizations are applied to a kernel subroutine from a real-world supersonic combustion simulation code, which intensively involves powering operations. The result shows that the performance of that subroutine is improved for 13.25 times on the Intel Xeon E5-2692 CPU.

关键词： Benchmark testing Arrays Libraries Runtime Signal processing algorithms Hardware

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Optimized deep belief networks on CUDA GPUs

Optimized deep belief networks on CUDA GPUs

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International Joint Conference on Neural Networks, IJCNN 2015

作者： Li, Teng Dou, Yong Jiang, Jingfei Wang, Yueqing Lv, Qi National Laboratory for Parallel and Distributed Processing National University of Defense and Technology Changsha China

ISBN: (纸本)9781479919604

A deep belief network (DBN) is an important branch of deep learning models and has been successfully applied in many machine learning and pattern recognition fields such as computer vision and speech recognition. However, the training of billions of parameters in DBN is computationally challenging for modern central processing units (CPUs). Many studies have reported the efficient implementations of the pre-training process of DBNs for graphics processing units (GPUs), but few studies have mentioned the fine-tuning process of DBNs. In this paper, we describe an efficient DBN implementation on the GPU, including the pre-training and fine-tuning processes. Experimental results show that our proposed method on the GPU (NVIDIA Tesla K40c) achieves up to 22 speedups on the pre-training process and 33 speedups on the fine-tuning processes compared with conventional CPU (Intel Core i7-4790K) implementations. Moreover, the performance of our algorithm is superior to that of the OpenBLAS library on the CPU and the CUBLAS library on the GPU. © 2015 IEEE.

关键词： Graphics processing unit

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Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Vector SIMD DSPs

Mod (2P-1) Shuffle Memory-Access Instructions for FFTs on Ve...

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IEEE Computer Society Annual Symposium on VLSI

作者： Sheng Liu Hanyan Chen Jianghua Wan Yaohua Wang College of Computer National University of Defense Technology Changsha Hunan China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781467390408

Binary Exchange Algorithm (BEA) always introduces excessive shuffle operations when mapping FFTs on vector SIMD DSPs. This can greatly restrict the overall performance. We propose a novel mod (2P-1) shuffle function and Mod-BEA algorithm (MBEA), which can halve the shuffle operation count and unify the shuffle mode. Such unified shuffle mode inspires us to propose a set of novel mod (2P-1) shuffle memory-access instructions, which can totally eliminate the shuffle operations. Experimental results show that the combination of MBEA and the proposed instructions can bring 17.2%-31.4% performance improvements at reasonable hardware cost, and compress the code size by about 30%.

关键词： Digital signal processing Hardware Pipelines Computer architecture Linearity Computers Software

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Implementation of a Fine-Grained parallel full pipeline Schnorr–Euchner sphere decoder algorithm accelerator on Field-Programmable gate array 4th

Implementation of a Fine-Grained parallel full pipeline Schn...

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4th International Conference on Computer Engineering and Networks, CENet2014

作者： Li, Shijie Guo, Lei Dou, Yong Jiang, Jingfei National laboratory for parallel and distributed processing National University of Defense Technology Changsha410073 China

ISBN: (纸本)9783319111032

A new parallel full pipeline accelerator implemented on fieldprogrammable gate array (FPGA) for the Schnorr–Euchner sphere decoding (SE– SD) algorithm is presented in this paper. We firstly transform the serial SE–SD algorithm into a parallel one. Afterwards, we use multiple processing elements (PEs) to deal with the workload (particularly for tree searching in the SE–SD algorithm) in parallel. Each separated SE–SD search workload is divided averagely. Each PE searches a sub-tree by using a multilevel pipeline to increase the data throughput, and the whole system obtains a batch of different input data chronologically. We select the number of PEs to distribute our system according to the hardware platform by using a distribution unit. We’ve successfully placed four PEs in an accelerator and eight accelerators in a single FPGA (XC6VLX240T). The system obtains remarkable benefit in changing the accelerate mode, including latency- and throughput-prior modes. © Springer International Publishing Switzerland 2015.

关键词： MIMO systems

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DIPP—An LLC replacement policy for on-chip dynamic heterogeneous multi-core architecture

DIPP—An LLC replacement policy for on-chip dynamic heteroge...

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International Conference of Young Computer Scientists, Engineers and Educators, ICYCSEE 2015

作者： Yang, Zhang Zuocheng, Xing Xiao, Ma Science and technology on Parallel and distributed processing laboratory National University of Defense Technology ChangSha China

ISBN: (纸本)9783662462478

As the big data era is coming, it brings new challenges to the massive data processing. A combination of GPU and CPU on chip is the trend to release the pressure of large scale computing. We found that there are different memory access characteristics between GPU and CPU. The most important one is that the programs of GPU include a large number of threads, which lead to higher access frequency in cache than the CPU programs. Although the LRU policy favors the programs with high memory access frequency, the programs of GPU can’t get the corresponding performance boost even more cache resources are provided. So LRU policy is not suitable for heterogeneous multi-core processor. Based on the different characteristics of GPU and CPU programs on memory access, this paper proposes an LLC dynamic replacement policy--DIPP (Dynamic Insertion/ Promotion Policy) for heterogeneous multi-core processors. The core idea of the replacement policy is to reduce the miss rate of the program and enhance the overall system performance by limiting the cache resources that GPU can acquire and reducing the thread interferences between programs. Experiments compare the DIPP replacement policy with LRU and we conduct a classified discussion according to the program results of GPU. Friendly programs enhance 23.29% on the average performance (using arithmetic mean). Large working sets programs can improve 13.95%, compute-intensive programs enhance 9.66% and stream class programs improve 3.8%. © Springer-Verlag Berlin Heidelberg 2015.

关键词： Graphics processing unit

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A data-driven mechanism for large-scale data distribution

A data-driven mechanism for large-scale data distribution

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Proceedings of the Biannual World Automation Congress

作者： Peichang Shi Yiying Li Bo Ding Longquan Jiang Hui Liu Jie Zhang National Key Laboratory of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha Hunan CN National Key Laboratory of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha 410073 China National University of Defense Technology Changsha Hunan CN China Electr. Equip. & Syst. Eng. Co. Ltd. China

As The integration of Physical space and cyberspace, the large-scale data distributing to diversification terminal which is geographical distribution of mass has become a huge challenge. When the data size can't be processed by the technology for traditional scope, how to deal with the user quality of service and efficient use of system resources has become an important issue of concern, with the resources becoming limited. This paper presents a data-driven mechanism for large-scale data distribution which is consists of four core part of the data production, data collection and pre-processing, data analysis engine, data consumption, aims to excavate the valuable information to improve the efficiency of resource use and accurate fault location for the Large-scale data distribution system. At the same time, this paper studies the resource scheduling optimization with analyzing data driven for the system behavior and Fault location with analyzing data-driven environment, which proves the effectiveness for the operation of the Large-scale data distribution system optimization by the data-driven working.

关键词： Servers Monitoring distributed databases Big data Real-time systems Business

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Enabling Tissue-Scale Cardiac Simulations Using Heterogeneous Computing on Tianhe-2

Enabling Tissue-Scale Cardiac Simulations Using Heterogeneou...

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International Conference on parallel and distributed Systems (ICPADS)

作者： Johannes Langguth Qiang Lan Namit Gaur Xing Cai Mei Wen Chun-Yuan Zhang Simula Research Laboratory Lysaker Norway College of Computer National University of Defense Technology Changsha China National Key Laboratory of Parallel and Distributed Processing Changsha China Department of Informatics University of Oslo Oslo Norway

ISBN: (纸本)9781509053827

We develop a simulator for 3D tissue of the human cardiac ventricle with a physiologically realistic cell model and deploy it on the supercomputer Tianhe-2. In order to attain the full performance of the heterogeneous CPU-Xeon Phi design, we use carefully optimized codes for both devices and combine them to obtain suitable load balancing. Using a large number of nodes, we are able to perform tissue-scale simulations of the electrical activity and calcium handling in millions of cells, at a level of detail that tracks the states of trillions of ryanodine receptors. We can thus simulate arrythmogenic spiral waves and other complex arrhythmogenic patterns which arise from calcium handling deficiencies in human cardiac ventricle tissue. Due to extensive code tuning and parallelization via OpenMP, MPI, and SCIF/COI, large scale simulations of 10 heartbeats can be performed in a matter of hours. Test results indicate excellent scalability, thus paving the way for detailed whole-heart simulations in future generations of leadership class supercomputers.

关键词： Calcium Computational modeling Mathematical model Performance evaluation Hardware Instruction sets Supercomputers

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Improving performance portability for GPU-specific Open CL kernels on multi-core/many-core CPUs by analysis-based transformations

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Frontiers of Information Technology & Electronic Engineering 2015年第11期16卷 899-916页

作者： Mei WEN Da-fei HUANG Chang-qing XUN Dong CHEN School of Computer National University of Defense Technology National Key Laboratory of Parallel and Distributed Processing

OpenCL is an open heterogeneous programming framework. Although OpenCL programs are func- tionally portable, they do not provide performance portability, so code transformation often plays an irreplaceable role. When adapting GPU-specific OpenCL kernels to run on multi-core/many-core CPUs, coarsening the thread granularity is necessary and thus has been extensively used. However, locality concerns exposed in GPU-specific OpenCL code are usually inherited without analysis, which may give side-effects on the CPU performance. Typi- cally, the use of OpenCL＇s local memory on multi-core/many-core CPUs may lead to an opposite performance effect, because local-memory arrays no longer match well with the hardware and the associated synchronizations are costly. To solve this dilemma, we actively analyze the memory access patterns using array-access descriptors derived from GPU-specific kernels, which can thus be adapted for CPUs by （1） removing all the unwanted local-memory arrays together with the obsolete barrier statements and （2） optimizing the coalesced kernel code with vectorization and locality re-exploitation. Moreover, we have developed an automated tool chain that makes this transformation of GPU-specific OpenCL kernels into a CPU-friendly form, which is accompanied with a scheduler that forms a new OpenCL runtime. Experiments show that the automated transformation can improve OpenCL kernel performance on a multi-core CPU by an average factor of 3.24. Satisfactory performance improvements axe also achieved on Intel＇s many-integrated-core coprocessor. The resultant performance on both architectures is better than or comparable with the corresponding OpenMP performance.

关键词： OpenCL Performance portability Multi-core/many-core CPU Analysis-based transformation

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