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Structure and method for hardware acceleration of variable data set management

Hunan Daxue Xuebao/Journal of Hunan University Natural Sciences 2013年第11 SUPPL.期40卷 68-73页

作者： Xu, Jin-Bo Dou, Yong Sun, Cai-Xia Dong, Ya-Zhuo Wang, Shao-Gang Lu, Ping-Jing Zhang, Jun College of Computer National Univ of Defense Technology Changsha Hunan 410073 China National Laboratory for Parallel and Distributed Processing National Univ of Defense Technology Changsha Hunan 410073 China Unit 91655 People's Liberation Army Beijing 100036 China

A general hardware structure was proposed to accelerate variable data set management, which was designed to accept instructions flexibly and accomplish the commonly used functions and some more complicated functions of the linked-list data structure .The structure can access the data based on both pointer and address mechanism. In order to fully utilize the limited memory resources, we proposed a memory recycle scheme to reuse the memory space where the data have been deleted. Experimental results on FPGA show that our proposal can accelerate the variable data set management. Only few hardware resources were used and it consumed pretty low power. Compared with the software linked-list structure in PC, our proposal in FPGA achieved high speedups.

关键词： Field programmable gate arrays (FPGA)

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Mining Software Profile across Multiple Repositories for Hierarchical Categorization

Mining Software Profile across Multiple Repositories for Hie...

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International Conference on Software Maintenance (ICSM)

作者： Tao Wang Huaimin Wang Gang Yin Charles X. Ling Xiang Li Peng Zou National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China Department of Computer Science The University of Western Ontario London Ontario Canada Academy of Equipment Beijing China

ISBN: (纸本)9781467352185

The large amounts of software repositories over the Internet are fundamentally changing the traditional paradigms of software maintenance. Efficient categorization of the massive projects for retrieving the relevant software in these repositories is of vital importance for Internet-based maintenance tasks such as solution searching, best practices learning and so on. Many previous works have been conducted on software categorization by mining source code or byte code, which are only verified on relatively small collections of projects with coarse-grained categories or clusters. However, Internet-based software maintenance requires finer-grained, more scalable and language-independent categorization approaches. In this paper, we propose a novel approach to hierarchically categorize software projects based on their online profiles across multiple repositories. We design a SVM-based categorization framework to classify the massive number of software hierarchically. To improve the categorization performance, we aggregate different types of profile attributes from multiple repositories and design a weighted combination strategy which assigns greater weights to more important attributes. Extensive experiments are carried out on more than 18,000 projects across three repositories. The results show that our approach achieves significant improvements by using weighted combination, and the overall precision, recall and F-Measure can reach 71.41%, 65.60% and 68.38% in appropriate settings. Compared to the previous work, our approach presents competitive results with 123 finer-grained and multi-layered categories. In contrast to those using source code or byte code, our approach is more effective for large-scale and language-independent software categorization.

关键词： Databases Collaboration Servers Software maintenance Internet Data mining

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NR-MPI: A Non-stop and Fault Resilient MPI

NR-MPI: A Non-stop and Fault Resilient MPI

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International Conference on parallel and distributed Systems (ICPADS)

作者： Guang Suo Yutong Lu Xiangke Liao Min Xie Hongjia Cao State Key Laboratory of High Performance Computing National University of Defense Technology Changsha Hunan Province China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha Hunan Province China

Fault resilience has became a major issue for HPC systems, in particular in the perspective of future E-scale systems, which will consist of millions of CPU cores and other components. Fault tolerant MPI was proposed to offer support of software level fault tolerance approaches. However, the widely used MPI implementations, such as MPICH and Mvapich2, provide limited support for fault tolerance. This paper proposes NR-MPI, a Non-stop and Fault Resilient MPI. NR-MPI implements the semantics of FT-MPI based on MPICH. Specifically, this paper focuses on failure detection in MPI library, online failure recovery of communicators for multiple failures, friendly programming interface extending for NR-MPI. Furthermore, to support failure recovery of applications, NR-MPI implements data backup and restore interfaces based on double in-memory checkpoint/restart. We conduct experiments with NPB benchmarks on TH-1A supercomputer. Experimental results show that NR-MPI based fault tolerant programs can recover from failures online without restarting, and the overhead is small even for applications with tens of thousands of cores.

关键词： Fault tolerance Fault tolerant systems Libraries Resource management Context Programming Semantics

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MPtostream:an OpenMP compiler for CPU-GPU heterogeneous parallel systems

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Science China(Information Sciences) 2012年第9期55卷 1961-1971页

作者： YANG XueJun,TANG Tao ,WANG GuiBin,JIA Jia & XU XinHai National laboratory for parallel and distributed processing,National University of Defense Technology,Changsha 410073,China 1. National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

In light of GPUs’ powerful floating-point operation capacity,heterogeneous parallel systems incorporating general purpose CPUs and GPUs have become a highlight in the research field of high performance computing(HPC).However,due to the complexity of programming on GPUs,porting a large number of existing scientific computing applications to the heterogeneous parallel systems remains a big *** OpenMP programming interface is widely adopted on multi-core CPUs in the field of scientific *** effectively inherit existing OpenMP applications and reduce the transplant cost,we extend OpenMP with a group of compiler directives,which explicitly divide tasks among the CPU and the GPU,and map time-consuming computing fragments to run on the GPU,thus dramatically simplifying the *** have designed and implemented MPtoStream,a compiler of the extended OpenMP for AMD’s stream processing *** experimental results show that programming with the extended directives deviates from programming with OpenMP by less than 11% modification and achieves significant speedup ranging from 3.1 to 17.3 on a heterogeneous system,incorporating an Intel Xeon E5405 CPU and an AMD FireStream 9250 GPU,over the execution on the Xeon CPU alone.

关键词： GPGPU stream OpenMP compiler

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Orthogonal Nonnegative Locally Linear Embedding

Orthogonal Nonnegative Locally Linear Embedding

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IEEE International Conference on Systems, Man, and Cybernetics

作者： Lei Wei Naiyang Guan Xiang Zhang Zhigang Luo Dacheng Tao National Laboratory for Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha 410073 P.R. China These authors contributed equally to this paper National Laboratory for Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha 410073 P.R. China Centre for Quantum Computation and Intelligence Systems and Faculty of Engineering and Information Technology University of Technology Sydney Sydney NSW 2007 Australia

ISBN: (纸本)9781479906505

Nonnegative matrix factorization (NMF) decomposes a nonnegative dataset X into two low-rank nonnegative factor matrices, i.e., W and H, by minimizing either Kullback-Leibler (KL) divergence or Euclidean distance between X and WH. NMF has been widely used in pattern recognition, data mining and computer vision because the non-negativity constraints on both W and H usually yield intuitive parts-based representation. However, NMF suffers from two problems: 1) it ignores geometric structure of dataset, and 2) it does not explicitly guarantee partsbased representation on any datasets. In this paper, we propose an orthogonal nonnegative locally linear embedding (ONLLE) method to overcome aforementioned problems. ONLLE assumes that each example embeds in its nearest neighbors and keeps such relationship in the learned subspace to preserve geometric structure of a dataset. For the purpose of learning parts-based representation, ONLLE explicitly incorporates an orthogonality constraint on the learned basis to keep its spatial locality. To optimize ONLLE, we applied an efficient fast gradient descent (FGD) method on Stiefel manifold which accelerates the popular multiplicative update rule (MUR). The experimental results on real-world datasets show that FGD converges much faster than MUR. To evaluate the effectiveness of ONLLE, we conduct both face recognition and image clustering on real-world datasets by comparing with the representative NMF methods.

关键词： Nonnegative matrix factorization Locally linear embedding Fast gradient descent Stiefel manifold Dataset Nonnegative matrix decomposition geometrical construction NMF protocol images embedding Flue gas desulfurization Nearest neighbor Orthogonal

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Latency-Aware Dynamic Voltage and Frequency Scaling on Many-Core Architectures for Data-Intensive Applications

Latency-Aware Dynamic Voltage and Frequency Scaling on Many-...

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International Conference on Cloud Computing and Big Data (CloudCom-Asia)

作者： Zhiquan Lai King Tin Lam Cho-Li Wang Jinshu Su Youliang Yan Wangbin Zhu National University of Defense Technology China The University of Hong Kong Hong Kong National Key Laboratory of Parallel and Distributed Processing (PDL) China Huawei Technologies Co. Ltd. Shenzhen China

Low power is the first-class design requirement for HPC systems. Dynamic voltage and frequency scaling (DVFS) has become the commonly used and efficient technology to achieve a trade-off between power consumption and system performance. However, most the prior work using DVFS did not take into account the latency of voltage/frequency scaling, which is a critical factor in real hardware determining the power efficiency of the power management algorithm. This paper, firstly, investigate the latency features of DVFS on a real many-core hardware platform. Secondly, we propose a latency-aware DVFS algorithm for profile-based power management to avoid aggressive power state transitions. At last, we evaluate our algorithm on Intel SCC platform using a data-intensive benchmark, Graph 500 benchmark. The experimental results not only show impressive potential for energy saving in data-intensive applications (up to 31% energy saving and 60% EDP reduction), but also evaluate the efficiency of our latency-aware DVFS algorithm which achieves 12.0% extra energy saving and 5.0% extra EDP reduction, moreover, increases the execution performance by 22.4%.

关键词： Benchmark testing Runtime Hardware Heuristic algorithms Time-frequency analysis Voltage measurement

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A fast successive over-relaxation algorithm for force-directed network graph drawing

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Science China(Information Sciences) 2012年第3期55卷 677-688页

作者： WANG YongXian & WANG ZhengHua National Key laboratory for parallel and distributed processing, National University of Defense Technology, Changsha 410073, China 1. National Key Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

Force-directed approach is one of the most widely used methods in graph drawing research. There are two main problems with the traditional force-directed algorithms. First, there is no mature theory to ensure the convergence of iteration sequence used in the algorithm and further, it is hard to estimate the rate of convergence even if the convergence is satisfied. Second, the running time cost is increased intolerablely in drawing largescale graphs, and therefore the advantages of the force-directed approach are limited in practice. This paper is focused on these problems and presents a sufficient condition for ensuring the convergence of iterations. We then develop a practical heuristic algorithm for speeding up the iteration in force-directed approach using a successive over-relaxation (SOR) strategy. The results of computational tests on the several benchmark graph datasets used widely in graph drawing research show that our algorithm can dramatically improve the performance of force-directed approach by decreasing both the number of iterations and running time, and is 1.5 times faster than the latter on average.

关键词： graph drawing graph layout successive over-relaxation force-directed algorithm

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Static Power Optimization for Homogeneous Multiple GPUs Based on Task Partition

Static Power Optimization for Homogeneous Multiple GPUs Base...

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2nd International Congress on Computer Applications and Computational Science (CACS 2011)

作者： Lin, Yisong Tang, Tao Wang, Guibin National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9783642283079;9783642283086

Recently, GPU has been widely used in High Performance Computing (HPC). In order to improve computational performance, several GPUs are integrated into one computer node in practical system. However, power consumption of GPUs is very high and becomes as bottleneck to its further development. In doing so, optimizing power consumption have been draw broad attention in the research area and industry community. In this paper, we present an energy optimization model considering performance constraint for homogeneous multi-GPUs, and propose a performance prediction model when task partitioning policy is specified. Experiment results validate that the model can accurately predict the execution of program for single or multiple GPUs, and thus reduce static power consumption by the guide of task partition.

关键词： Electric power utilization

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SPICE modeling of memristors with multilevel resistance states

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Chinese Physics B 2012年第9期21卷 594-600页

作者：方旭东唐玉华吴俊杰 National Laboratory for Parallel and Distributed Processing School of ComputerNational University of Defense Technology Department of Computer Science and Technology School of ComputerNational University of Defense Technology

With CMOS technologies approaching the scaling ceiling, novel memory technologies have thrived in recent years, among which the memristor is a rather promising candidate for future resistive memory （RRAM）. Memristor＇s potential to store multiple bits of information as different resistance levels allows its application in multilevel cell （MCL） tech- nology, which can significantly increase the memory capacity. However, most existing memristor models are built for binary or continuous memristance switching. In this paper, we propose the simulation program with integrated circuits emphasis （SPICE） modeling of charge-controlled and flux-controlled memristors with multilevel resistance states based on the memristance versus state map. In our model, the memristance switches abruptly between neighboring resistance states. The proposed model allows users to easily set the number of the resistance levels as parameters, and provides the predictability of resistance switching time if the input current/voltage waveform is given. The functionality of our models has been validated in HSPICE. The models can be used in multilevel RRAM modeling as well as in artificial neural network simulations.

关键词： memristor multilevel cell SPICE model

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PartialRC: A Partial Recomputing Method for Efficient Fault Recovery on GPGPUs

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Journal of Computer Science & Technology 2012年第2期27卷 240-255页

作者：徐新海杨学军薛京灵林宇斐林一松 National Laboratory for Parallel and Distributed Processing School of ComputerNational University of Defense Technology Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales

GPGPUs are increasingly being used to as performance accelerators for HPC （High Performance Computing） applications in CPU/GPU heterogeneous computing systems, including TianHe-1A, the world＇s fastest supercomputer in the TOP500 list, built at NUDT （National University of Defense Technology） last year. However, despite their performance advantages, GPGPUs do not provide built-in fault-tolerant mechanisms to offer reliability guarantees required by many HPC applications. By analyzing the SIMT （single-instruction, multiple-thread） characteristics of programs running on GPGPUs, we have developed PartialRC, a new checkpoint-based compiler-directed partial recomputing method, for achieving efficient fault recovery by leveraging the phenomenal computing power of GPGPUs. In this paper, we introduce our PartialRC method that recovers from errors detected in a code region by partially re-computing the region, describe a checkpoint-based faulttolerance framework developed on PartialRC, and discuss an implementation on the CUDA platform. Validation using a range of representative CUDA programs on NVIDIA GPGPUs against FullRC （a traditional full-recomputing Checkpoint-Rollback-Restart fault recovery method for CPUs） shows that PartialRC reduces significantly the fault recovery overheads incurred by FullRC, by 73.5% when errors occur earlier during execution and 74.6% when errors occur later on average. In addition, PartialRC also reduces error detection overheads incurred by FullRC during fault recovery while incurring negligible performance overheads when no fault happens.

关键词： GPGPU partial recomputing fault tolerance CUDA checkpointing

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