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Superscalar communication: A runtime optimization for distributed applications

Science China(Information Sciences) 2010年第10期53卷 1931-1946页

作者： LI HuiBa , LIU ShengYun, PENG YuXing, LI DongSheng, ZHOU HangJun & LU XiCheng National laboratory for parallel and distributed processing, National University of Defense Technology, Changsha 410073, China 1. National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

Building distributed applications is difficult mostly because of concurrency management. Existing approaches primarily include events and threads. Researchers and developers have been debating for decades to prove which is superior. Although the conclusion is far from obvious, this long debate clearly shows that neither of them is perfect. One of the problems is that they are both complex and error-prone. Both events and threads need the programmers to explicitly manage concurrencies, and we believe it is just the source of difficulties. In this paper, we propose a novel approach—superscalar communication, in which concurrencies are automatically managed by the runtime system. It dynamically analyzes the programs to discover potential concurrency opportunities; and it dynamically schedules the communication and the computation tasks, resulting in automatic concurrent execution. This approach is inspired by the idea of superscalar technology in modern microprocessors, which dynamically exploits instruction-level parallelism. However, hardware superscalar algorithms do not fit software in many aspects, thus we have to design a new scheme completely from scratch. Superscalar communication is a runtime extension with no modification to the language, compiler or byte code, so it is good at backward compatibility. Superscalar communication is likely to begin a brand new research area in systems software, which is characterized by dynamic optimization for networking programs.

关键词： network programming concurrency event thread superscalar

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An Energy-Efficient Scheduling Algorithm for Sporadic Real-Time Tasks in Multiprocessor Systems

An Energy-Efficient Scheduling Algorithm for Sporadic Real-T...

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IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Dong-Song Zhang Fang-Yuan Chen Hong-Hua Li Shi-Yao Jin De-Ke Guo National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China School of Computing Science Simon Fraser University Burnaby BC Canada National Laboratory for Information System Engineering School of Information Systems and Management National University of Defense Technology Changsha China

As the energy consumption of embedded multiprocessor systems becomes increasingly prominent, the real-time energy-efficient scheduling in multiprocessor systems becomes an urgent problem to reduce the system energy consumption while meeting real-time constraints. For a multiprocessor with independent DVFS and DPM at each processor, this paper proposes an energy-efficient real-time scheduling algorithm named LRE-DVFS-EACH, based on LRE-TL which is an optimal real-time scheduling algorithm for sporadic tasks. LRE-DVFS-EACH utilizes the concept of TL plane and the idea of fluid scheduling to dynamically scale the voltage and frequency of processors at the initial time of each TL plane as well as the release time of a sporadic task in each TL plane. Consequently, LRE-DVFS-EACH can obtain a reasonable tradeoff between the real-time constraints and the energy saving. LRE-DVFS-EACH is also adaptive to the change of workload caused by the dynamic release of sporadic tasks, which can obtain more energy savings. The experimental results show that compared with existing algorithms, LRE-DVFS-EACH can not only guarantee the optimal feasibility of sporadic tasks, but also achieve more energy savings in all cases, especially in the case of high workloads.

关键词： Real time systems Scheduling algorithm Time frequency analysis Scheduling Heuristic algorithms Power demand

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FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing 10

FPGA accelerating double/quad-double high precision floating...

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24th ACM International Conference on Supercomputing, ICS'10

作者： Dou, Yong Lei, Yuanwu Wu, Guiming Guo, Song Zhou, Jie Shen, Li National Laboratory for Parallel and Distributed Processing NUDT Changsha 410073 China

ISBN: (纸本)9781450300186

In this paper we explore the capability and flexibility of FPGA solutions in a sense to accelerate scientific computing applications which require very high precision arithmetic, based on 128-bit or even 256-bit floating-point number representation. This paper addresses the accuracy when performing LU decomposition on large-scale matrices. In future ExaScale computing environments, accuracy errors are expected to increase up to a level which leaves only 11 significant bits in the mantissa. This is caused by the required large amount of accumulation operations which are in the order of O(n 3). Using exact long fixed-point numbers instead of usual floatingpoint numbers in the accumulation process, leads to exact accumulation results with only one bit error, originated by the rounding in the last normalization step. We have developed two types of High Precision Multiplication and Accumulation (HP-MAC), for Double-Double (128 bits) and Quad-Double (256 bits) floating-point, respectively, and implemented them into FPGA devices. We propose a two-level RAM banks scheme to store and add long fixed-point numbers with minimized crucial data paths lengths. We also introduce a scheme of partial summation to enhance the pipeline throughput of MAC operations, by dividing the summation function into 4 partial operations, processed in 4 banks. To prove the concept, we prototyped six 128-bit HP-MAC units into a Xilinx Virtex-5 XC5VLX330 FPGA chip and performed LU decomposition. The experimental results show accuracy improvement of 10 to 24 bits, compared to a software approach with similar precision arithmetic. Moreover, our LU decomposition implementation, based on FPGA running at 133MHz, achieves 29X - 56X better performance and much lower power consumption compared to the use of a software-based library running on an Intel Core2 Quad Q8200 CPU at 2.33GHz. © 2010 ACM.

关键词： Field programmable gate arrays (FPGA)

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FPQRNA: Hardware-accelerated qrna package for noncoding rna gene detecting on FPGA

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Journal of Bioinformatics and Computational Biology 2010年第4期8卷 743-761页

作者： Xia, Fei Dou, Yong Lei, Guo-Qing National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

Noncoding RNAs (ncRNAs) have important functional roles in biological processes and have become a central research interest in modern molecular biology. However, how to find ncRNA attracts much more attention since ncRNA gene sequences do not have strong statistical signals, unlike protein coding genes. QRNA is a powerful program and has been widely used as an efficient analysis tool to detect ncRNA gene at present. Unfortunately, the O(L ³) computing requirements and complicated data dependency greatly limit the usefulness of QRNA package with the explosion in gene database. In this paper, we present a fine-grained parallel QRNA prototype system, FPQRNA, for accelerating ncRNA gene detection application on FPGA chip. We propose a systolic-like array architecture with multiple PEs (processing Elements). We partition the tasks by columns and assign tasks to PEs for load balance. We exploit data reuse schemes to reduce the need to load matrices from external memory. The experimental results show a speedup factor of more than 18× over the QRNA - 2.0.3c software running on a PC platform with AMD Phenom 9650 Quad CPU for pairwise sequence alignment with 996 residues, however the power consumption of our FPGA accelerator is only about 30% of that of the general-purpose microprocessors. © 2010 Imperial College Press.

关键词： Bioinformatics fine-grained parallelism FPGA hardware accelerator noncoding RNA

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A review on the churn character of P2P networks

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Jisuanji Xuebao/Chinese Journal of Computers 2011年第9期34卷 1563-1577页

作者： Fu, Zhi-Peng Wang, Huai-Min Shi, Dian-Xi Zou, Peng School of Computer Science National University of Defense Technology Changsha 410073 China National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

P2P application is one of the most popular applications in the Internet, but its performance is badly influenced by the churn character-the nodes continuous arrival and departure. On the basis of introducing the origin of the churn, the definition of it and its influences to the P2P system performance, we minutely describe the research on the statistical properties, and discover some dynamic law including nodes' session time generally obey the heavy-tailed distribution. Then we detail the measurement methods. For passive monitoring, active monitoring, sample and so on, we present the advantages and disadvantages of each method, and explain the corresponding improving method to enhance the accuracy of the measurement. After that we elaborate the resilience strategies to the churn. Towards the neighbor selection, failure recovery, replica maintenance, link lifetime maintenance and so on, we present also the advantage and disadvantage of each strategy, and present our view to each of aspects. Finally, the summary and prospect of the future research are given.

关键词： Peer to peer networks

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A data communication scheduler for stream programs on CPU-GPU platform

A data communication scheduler for stream programs on CPU-GP...

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10th IEEE International Conference on Computer and Information Technology, CIT-2010, 7th IEEE International Conference on Embedded Software and Systems, ICESS-2010, 10th IEEE Int. Conf. Scalable Computing and Communications, ScalCom-2010

作者： Tang, Tao Xu, Xinhai Lin, Yisong National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9780769541082

In recent years, heterogeneous parallel system have become a focus research area in high performance computing field. Generally,in a heterogeneous parallel system, CPU provides the basic computing environment and special purpose accelerator (GPU in this paper) provides high computing performance. However, the overall performance of the system is prone to be limited by the data communication between the CPU and the GPU. Data communication is typically used to synchronize the array on the CPU and the stream (in AMD's terminology) on the GPU. In many cases, programmers just add data synchronization for each GPU invoking independently. It is easy to program in this manner but much redundant communication may be introduced, which will dramatically degrade the overall performance. To alleviate this problem, based on the stream programming model, we propose a heuristic data communication schedule approach in this paper. By analyzing the state transition of stream/array data pair, relaxing the synchronization strategy conditionally and considering optimization for branch and loop control structure, our approach can significantly reduce the redundant data communication in most cases. © 2010 IEEE.

关键词： Graphics processing unit

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Automatic concurrency management for distributed applications

Automatic concurrency management for distributed application...

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15th IEEE Symposium on Computers and Communications, ISCC 2010

作者： Li, Huiba Liu, Shengyun Peng, Yuxing Li, Dongsheng National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424477555

Building distributed applications is difficult mostly because of concurrency management. Existing approaches primarily include events and threads. Researchers and developers have been debating for decades to prove which is superior. Although the conclusion is far from obvious, this long debate clearly shows that neither of them is perfect. One of the problems is that they are both complex and error-prone. Both events and threads need the programmers to explicitly manage concurrency, and we believe it is just the source of difficulties. In this paper, we propose a novel approach-automatic concurrency management by the runtime system. It dynamically analyzes the programs to discover potential concurrency opportunities;and it dynamically schedules the communication and the computation tasks, resulting in automatic concurrent execution. This approach is inspired by the instruction scheduling technologies used in modern microprocessors, which dynamically exploits instruction-level parallelism. However, hardware scheduling algorithms do not fit software in many aspects, thus we have to design a new scheme completely from scratch. automatic concurrency management is a runtime technique with no modification to the language, compiler or byte code, so it is good at backward compatibility. It is essentially a dynamic optimization for networking programs. © 2010 IEEE.

关键词： Scheduling algorithms

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Design and practice on iVCE for memory system

Design and practice on iVCE for memory system

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16th IEEE International Conference on parallel and distributed Systems, ICPADS 2010

作者： Chu, Rui Tian, Tian Lin, Zhenli National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9780769543079

As one of the components in iVCE software platform, iVCE/M devotes to the performance improvement of the I/O-intensive and memory-intensive applications with efficient aggregation of distributed memory resources. To facilitate the deployment of iVCE/M, the data locating algorithm with balanced time and space cost, as well as the transparent interface for the legacy applications without code modification, are both significant in the implementation of iVCE/M. We propose the logarithmic search tree based client-side metadata structure to accelerate the data locating using moderate memory consumption, the implicit I/O redirection mechanism, and the implementation of iVCE/M based disk cache system. The experiments with cross domain emulation prove that the scheme is applicable to exploit the distributed memory resources for applications with small granularity I/O accesses. © 2010 IEEE.

关键词： Application programs

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HiAL-Ckpt: A hierarchical application-level checkpointing for CPU-GPU hybrid systems

HiAL-Ckpt: A hierarchical application-level checkpointing fo...

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International Conference on Computer Science and Education

作者： Xu, Xinhai Lin, Yufei Tang, Tao Lin, Yisong National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424460052

In light of its powerful computing capacity and high energy efficiency, GPU (graphics processing unit) has become a focus in the research field of HPC (High Performance Computing). CPU-GPU heterogeneous parallel systems have become a new development trend of super-computer. However, the inherent unreliability of the GPU hardware deteriorates the reliability of super-computer. We have researched on the fault-tolerance(FT) technique for CPU-GPU heterogeneous parallel systems, and introduced a new checkpointing mechanism, i.e., the hierarchical application-level checkpointing, for such systems. The basic idea of this new checkpointing mechanism is checkpointing at two independent levels, i.e., CPU level and GPU level, to tolerate CPU and GPU faults respectively. Based on the idea, we have also designed and implemented a hierarchical application-level checkpointing tool "HiAL-Ckpt". Using this tool, programmers can insert two kinds of directives, i.e., CPU directives and GPU directives into a program, and the compiler will transform the directives into CPU or GPU checkpointing codes according to their nature. From the case study of SWIM, a test bench from spec2000 benchmark suite, we have demonstrated the validity of the hierarchical application-level checkpointing technique. The experimental results show that the falut-tolerance temporal cost of HiAL-Ckpt for SWIM is only 2.25%, compared with the executing time of SWIM without any FT work. ©2010 IEEE.

关键词： Graphics processing unit

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Mapping OpenMP concepts to the stream programming model

Mapping OpenMP concepts to the stream programming model

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International Conference on Computer Science and Education

作者： Tang, Tao Lin, Yisong Ren, Xiaoguang National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424460052

OpenMP is a widely used parallel programming model on traditional multi-core processors. Generally, OpenMP is used to develop fine-grained parallelism through a multithread model. Stream programming model is a new kind of parallel programming model for stream architectures. OpenMP bears a resemblance to the stream programming model at some level. The transformation between the two models has attracted much attention from the research community, since it is the foundation of porting programs between the two architectures. Most related researches focus on the efficiency of porting existing parallel programs to the new architectures such as GPUs. Very few of these studies, however, focus on the portative problem systematically, namely, what kind of parallel programs can be or should be transplanted into stream programs and mapped to run on the stream processors. In this paper, we study the mapping relationship of parallel mechanism in OpenMP to the stream programming model, and point out those parallel mechanisms in OpenMP that are infeasible or undesirable for stream programs. By analyzing two typical benchmarks, we draw the conclusion that a majority of scientific applications are suitable to be mapped to the stream programming model. Our conclusion effectively validates the idea of accelerating scientific applications with the stream processors. ©2010 IEEE.

关键词： Mapping

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