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Two improved GPU acceleration strategies for force-directed graph layout

Two improved GPU acceleration strategies for force-directed ...

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International Conference on Computer Application and System Modeling

作者： Wang, Yong-Xian Li, Zong-Zhe Yao, Lu Cao, Wei Wang, Zheng-Hua National Key Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9781424472369

Force directed approach is one of the most widely used methods in graph drawing research. However, the running time is increased intolerablely along with the enlargement of the graph size, which restricts the algorithm's practicability. By the aid of GPU (graphics processing unit) computing platform, we can speed-up the graph layout with low cost, but the existing GPU implementation mainly employees an "one-by-one" style to update the vertex' coordination per iteration, which has a lower convergent rate than the "batch" style which is instead used commonly in traditional CPU implementation. As a result, the aesthetics of graph layout would be decreased if the total running time is restricted. It is hard to achieve both a high speedup factor of GPU over CPU and a high convergent rate in existing GPU computing implementation. In order to solve this problem partially, this paper presents two new strategies to implement the large-scale graph layout on CPU+GPU heteromerous platform to accelerate the force directed layout for graph drawing problem. The numerical computation results show that our GPU implementation can dramatically improve the performance of force-direct layout and is 20 times on a NVIDIA GeForce 9800 GT GPU at 1.44 GHz faster than the one on single-CPU core of Intel Pentium 4 PC at 3.0 GHz for the graph layout with moderate size (typically 1000 vertices). © 2010 IEEE.

关键词： Graphics processing unit

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An efficient load balancing method for constant degree P2P systems

An efficient load balancing method for constant degree P2P s...

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2010 International Conference on Computer Design and Applications, ICCDA 2010

作者： Wang, XiaoHai Peng, YuXing Li, DongSheng National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9781424471638

Constant degree P2P systems are turning into the P2P domain's promising hotspot due to their good properties. However, it is often hard to convert a standard constant degree digraph to a flexible DHT schema adapting to dynamic P2P environments. Thus, most research about constant degree P2P focus on DHT's construction and maintenance, while leaving optimization and supporting to upper-layer application behind, such as complex query, load balance, etc. Combining constant degree topology's bit-shift routing schema, we presents an efficient load balancing algorithm based on Reverse Spanning Tree (REST) for constant degree P2P systems. Using the statistic information in joining process, REST judges how many Virtual Servers that a new join super peer can run, and then join all virtual servers evenly and fast with low cost based on the Spanning Tree Peer Set. Experimental results show, without additional data structure, REST keeps the constant degree P2P system load-balanced by assuring each peer of owning a key space proportional to its capability. © 2010 IEEE.

关键词： Trees (mathematics)

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Dynamic program Behavior Identification for high performance CMPs with private LLCs

Dynamic program Behavior Identification for high performance...

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作者： Jia, Xiaomin Lu, Pingjing Sun, Caixia Zhang, Minxuan National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology China

Chip Multi-Processors (CMPs) emerge as a mainstream architectural design alternative for high performance parallel and distributed computing. Last Level Cache (LLC) management is critical to CMPs because off-chip accesses often require a long latency. Due to its short access latency, well performance isolation and easy scalability, private cache is an attractive design alternative for LLC of CMPs. This paper proposes program Behavior Identification-based Cache Sharing (BICS) for LLC management. BICS is based on a private cache organization for the shorter access latency. Meanwhile, BICS tries to simulate a shared cache organization by allowing evicted blocks of one private LLC to be saved at peer LLCs. This technique is called spilling. BICS identifies cache behavior types of applications at runtime. When a cache block is evicted from a private LLC, cache behavior characteristics of the local application are evaluated so as to determine whether the block is to be spilled. Spilled blocks are allowed to replace some valid blocks of the peer LLCs as long as the interference is within a reasonable level. Experimental results using a full system CMP simulator show that BICS improves the overall throughput by as much as 14.5%, 12.6%, 11.0% and 11.7% (on average 8.8%, 4.8%, 4.0% and 6.8%) over private cache, shared cache, Utility-based Cache Partitioning (UCP) scheme and the baseline spilling-based organization Cooperative Caching (CC) respectively on a 4-core CMP for SPEC CPU2006 benchmarks. Copyright© 2010.

关键词： Integrated circuit design

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Nexus: Speculative execution for event-driven networking programs

Nexus: Speculative execution for event-driven networking pro...

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16th IEEE International Conference on parallel and distributed Systems, ICPADS 2010

作者： Li, Huiba Lu, Xicheng Peng, Yuxing National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769543079

The efficiency of communication is a key factor to the performance of networking applications, and concurrent communication is an important approach to the efficiency of communication. However, many concurrency opportunities are very difficult to exploit because they depend on some undeterministic conditions. If these conditions are highly predictable, speculative execution can be a very effective approach to cope with the uncertainties. Existing researches on speculation seldom target at networking systems, and none of them can handle the event-driven model that is very popular in such systems. In this paper, we propose Nexus, a novel speculation scheme that supports event-driven networking applications. Nexus analyzes the dependence relationship of events, and performs speculation according to the duality of events and threads. Evaluation on a prototype implementation of nexus shows that this approach can significantly reduces the time needed to complete an event-driven program. © 2010 IEEE.

关键词： Efficiency

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Evaluating the performance and accuracy impact of trace generation to the bigsim emulator

Evaluating the performance and accuracy impact of trace gene...

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10th IEEE International Conference on Computer and Information Technology, CIT-2010, 7th IEEE International Conference on Embedded Software and Systems, ICESS-2010, 10th IEEE Int. Conf. Scalable Computing and Communications, ScalCom-2010

作者： Che, Yonggang Xu, Chuanfu Lu, Pingjing National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9780769541082

This paper quantitatively studies the trace effects to the performance and accuracy of the BigSim Emulator, a scalable parallel emulator for large-scale computers. To assess the accuracy effect we modify the emulator code to collect the predicted computation time. Four MPI programs with different computation to communication ratios are used as benchmarks. The emulation time and the predicted computation time, both when trace generation are enabled and disabled, are collected on two parallel host machines. The results show that although the BigSim Emulator only traces communication events and dependencies, trace generation still evidently degrades the emulation performance for programs with high communication to computation ratios. Trace generation also significantly affects the accuracy of the predicted computation time for communication intensive programs, which is an issue that can not be overlooked. © 2010 IEEE.

关键词： BigSim emulator MPI programs digital simulation emulator code large scale computers message passing parallel host machines parallel programming performance evaluation scalable parallel emulator trace generation accuracy impact

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Feature preserving consolidation for unorganized point clouds

Feature preserving consolidation for unorganized point cloud...

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IEEE International Conference on Progress in Informatics and Computing (PIC)

作者： Li, Bao Jiang, Wei Cheng, Zhiquan Dang, Gang Jin, Shiyao National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9781424467860

We introduce a novel method for the consolidation of unorganized point clouds with noise, outliers, non-uniformities as well as sharp features. This method is feature preserving, in the sense that given an initial estimation of normal, it is able to recover the sharp features contained in the original geometric data which are usually contaminated during the acquisition. The key ingredient of our approach is a weighting term from normal space as an effective complement to the recently proposed consolidation techniques. Moreover, a normal mollification step is employed during the consolidation to get normal information respecting sharp features besides the position of each point. Experiments on both synthetic and real-world scanned models validate the ability of our approach in producing denoised, evenly distributed and feature preserving point clouds, which are preferred by most surface reconstruction methods. ©2010 IEEE.

关键词： Consolidation Feature preserving Point clouds Sharp features

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Link scheduling in wireless networks with successive interference cancellation

Link scheduling in wireless networks with successive interfe...

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International Conference on Mobile Ad-hoc and Sensor Networks

作者： Lv, Shaohe Wang, Xiaodong Zhou, Xingming National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha Hunan 410073 China

ISBN: (纸本)9780769543154

Successive interference cancellation (SIC) is an effective technique of multipacket reception to combat interference. As not all collision are resolvable, careful transmission coordination is required. We study link scheduling in wireless networks with SIC at the physical layer. A new model, simultaneity graph (SG), is proposed to characterize the link correlation introduced by SIC. Then two new scheduling schemes are presented: 1) a slotoriented scheme which assigns a maximal feasible link set to a time slot and 2) a link-oriented scheme which assigns each link a sufficient number of slots. The performance is evaluated by simulations and the results demonstrate that the throughput gain is on average 50% and up to 110% over IEEE 802.11. The complexity of SG is only a bit higher than that of the available widely-used models (e.g., conflict graph). © 2010 IEEE.

关键词： Wireless networks

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Automatic Data Distribution for Improving Data Locality on the Cell BE Architecture

Automatic Data Distribution for Improving Data Locality on t...

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22nd International Workshop on Languages and Compilers for parallel Computing

作者： Wang, Miao Bodin, Francois Matz, Sebastien National Laboratory for Parallel and Distributed Processing NUDT China CAPS Entreprise Rennes France University of Rennes 1 Rennes France

ISBN: (纸本)9783642133732

Multicore systems provide potential to improve the performance of the applications. However, substantial programming effort is required to exploit the power of the parallelism. This paper presents a single source compiler to map the data-parallel programs onto Cell Broadband Engine. Based on the distributed memory model, the compiler performs automatic data distribution and generates SPMD programs with message-passing primitives for Cell. We evaluate our compiler using a range of computation intensive benchmarks, high performance is achieved on Cell platform. In contrast to OpenMP, our method can fully exploit data locality through managing the shared data using inter-processor communication instead of accessing main memory, which significantly reduces the off-chip memory access overhead.

关键词： Message passing

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A case study of SWIM: Optimization of memory intensive application on GPGPU

A case study of SWIM: Optimization of memory intensive appli...

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International Symposium on parallel Architectures, Algorithms, and Programming

作者： Yi, Wei Tang, Yuhua Wang, Guibin Fang, Xudong National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9780769543123

Recently, GPGPU has been adopted well in the High Performance Computing (HPC) field. The limited global memory bandwidth poses a great challenge to many GPGPU programmers trying to exploit parallelism within the CPUGPU heterogeneous platform. In this paper, we choose SWIM, a typical memory intensive application from the SPEC OMP 2001 benchmark suite, for case study. We attempt to optimize the performance and energy consumption of the application utilizing different memory access mechanisms and present optimization methods including matrix transposition and kernel fusion. The experimental results on the Intel CoreTM i920 CPU plus GeForce GTX 295 platform shows that, the proposed optimizing methods achieve a speedup of 8.7X over the original OpenMP program and reduce the energy consumption by 83% for the problem size of 2048*2048. © 2010 IEEE.

关键词： Energy utilization

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Accelerating MatLab code using GPU: A review of tools and strategies

Accelerating MatLab code using GPU: A review of tools and st...

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International Conference on Artificial Intelligence, Management Science and Electronic Commerce (AIMSEC)

作者： Baida Zhang Shuai Xu Feng Zhang Yuan Bi Linqi Huang National laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China Department of Information Engineering Academy of Armored Forces Engineering Beijing China Inspur (Beijing) Electronic Information Industry Company Limited Beijing China Naval Academy of Armament Beijing China School of Resources and Safety Engineering Central South University Changsha China

Lots of toolboxes of accelerating MatLab using GPU are available now[1], but, users are confused by which toolbox is best suitable for a particular task. Three toolboxes-Jacket, GPUmat, and parallel Computing Toolbox of MatLab are selected. For each toolbox, its advantages and pitfalls are reviewed, with an aim to allow the reader to identify which toolbox is appropriate for a given task. Strategies of whether a function should execute on GPU are given after a formula analysis. The analysis is also a framework for program automatically decides which function is cost-efficient to execute on GPU. A series of benchmark of different types of computing, including data transfer between GPU and CPU, data matrix Generation, matrix operation and GPU functions were tested in all three toolboxes. And the results show that Jacket is the best one. Some advices to improve the performance of toolboxes are given in the end.

关键词： Graphics processing unit Acceleration parallel processing Computer architecture Conferences Licenses MATLAB

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