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Survey of software environments for parallel distributed processing: parallel programming education on real life target systems using production oriented software tools

Survey of software environments for parallel distributed pro...

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Pan-Hellenic Conference on Informatics

作者： Delistavrou, Constantinos T. Margaritis, Konstantinos G. Department of Applied Informatics Parallel and Distributed Processing Laboratory University of Macedonia 156 Egnatia Street 54006 Thessaloniki Greece

ISBN: (纸本)9780769541723

parallel programming is the future of computer science. Now days shift to parallel processing makes it even more useful. This research effort aims at helping parallelism education on real life target systems, using production oriented software tools. On its beginning, a survey of software environments for parallel programming is presented. The surveyed software environments are categorized according to their main function. An identity is synthesized for each environment by software and project attributes. Based on it and a set of proper criteria there are selected two groups of tools, those of primary and those of secondary interest for this research. An analysis of functional characteristics is performed for both groups. From the first group an open source software environment is chosen as the basis platform that will be enriched with education oriented enhancements. The characteristics analysis is exploited for the proposal of a research and development framework. Its target is the support of parallel programming, on real life target systems, using production oriented software environments. © 2010 IEEE.

关键词： parallel programming

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Sim-spm: A simplescalar-based simulator for multi-level SPM memory hierarchy architecture

Sim-spm: A simplescalar-based simulator for multi-level SPM ...

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IEEE International Conference on High Performance Computing and Communication

作者： Ren, Xiaoguang Tang, Yuhua Tang, Tao Ye, Sen Wang, Huiquan Zhou, Jing National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan 410073 China

ISBN: (纸本)9780769542140

As a fast on-chip SRAM managed by software (the application and/or compiler), Scratchpad Memory (SPM) is widely used in many fields. This paper presents a SimpleScalar-based multi-level SPM memory hierarchy architecture simulator Sim-spm. We simulate the hardware of the multi-level SPM memory hierarchy successfully by extending Sim-outorder, which is an out-of-order simulator from SimpleScalar. Through the simulating memory method, the simulation framework of the multi-level SPM memory hierarchy has been built under the existing ISA (Instruction Set Architecture), which largely reduces the requirement to modify the existing compiler. The experimental results show that Sim-spm can accurately simulate the running state of the processor with a multi-level SPM memory hierarchy architecture, and it has a good prospect for the research of multi-level SPM memory hierarchy architecture. © 2010 IEEE.

关键词： Simulators

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Media access control protocol based on hybrid antennas in ad hoc networks

Media access control protocol based on hybrid antennas in ad...

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International Conference on Autonomic and Trusted Computing

作者： Ding, Yanrong Wang, Xiaodong Shen, Hu Guo, Pengyu National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769542720

Nested Circular Directional MAC, a modified medium access control protocol of DMAC protocol, is proposed in this paper to support both directional antennas and omni-directional antennas simultaneously in one Ad Hoc network. Omni-directional antennas follow the RTS/CTS mechanism which is multi-hop and directional antennas follow the DRTS/DCTS mechanism, ensuring the asymmetric communication effectively. In order to resolve new deafness problem and hidden terminal problem, the directional antennas also use circular DRTS and nested antenna circumrotation. Simulation results show that NCDMAC supports hybrid antennas effectively and is better than MMAC and Circular-MAC in terms of increasing throughput, but it also increases the communication delay. © 2010 IEEE.

关键词： Ad hoc networks

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Stigmergic collaboration: A sign-based perspective of stigmergy

Stigmergic collaboration: A sign-based perspective of stigme...

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2010 International Conference on Intelligent Computation Technology and Automation, ICICTA 2010

作者： Ren, Chuanjun Huang, Hongbing Jin, Shiyao National Laboratory for Parallel and Distributed Processing College of Computer Science National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769540771

Insects build architecturally complex nests and search for remote food by collaboration work despite their limited sensors, minimal individual intelligence and the lack of a central control system. Insets' collaborations emerge as a response of the individual insects to Stigmergy. A sign-based model of Stigmergy to discuss collaboration is proposed in this paper where we picked up "sign" as a key notion to understand it. Therefore, sign is the link of all the components in a Stigmergic complex adaptive system. Based on this understanding, we propose a definition that reveals the nature of signs and exploit the significations and relationships carried by the notion of sign. Then, a sign-based model of Stigmergy is consequently reached, which captures the essentials of Stigmergy. A basic architecture of Stigmergy as well as its constituents are presented and discussed. At last, some applications of the model are discussed. © 2010 Crown Copyright.

关键词： CAS Collaboration Emergence Sign Stigmergy Emergence Volatile Oils Insecta central control system

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Metal interference analysis and design rules of on chip antennas for wireless interconnect

Metal interference analysis and design rules of on chip ante...

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International Symposium on Signals, Systems and Electronics

作者： He, Xiaowei Zhang, Minxuan Li, Jinwen Li, Shaoqing National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan 410073 China

ISBN: (纸本)9781424463558

The influence of on-chip metal interconnections, power grids, heat sink together with packaging, and metal dummy fills on the transmission characteristics of a 2mm-long integrated dipole antenna pair has been investigated in this paper. These metal structures and placements have been classified and particular simulations are performed to explore the interference effects of neighboring various metal structures on transmission gain, phase, impedance and radiation pattern for on-chip dipole antenna pair. By virtue of the experimental results and analyses, several experiential linear expressions for antenna pair gain and phase in interference circumstances are obtained using numerical fit. A set of design rules is concluded accordingly for guiding on-chip antenna layout and design targeting wireless interconnect. © 2010 IEEE.

关键词： Dipole antennas

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RETRACTED ARTICLE: parallel block multigrid preconditioner for 3D navier-stokes equations on unstructured grids

RETRACTED ARTICLE: Parallel block multigrid preconditioner f...

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作者： Li, Zongzhe Lu, Yao Cao, Wei Wang, Yongxian Wang, Zhenghua Parallel and Distributed Processing for National Laboratory School of Computer Science National University of Defence Lechnology Changsha Hunan 410073 China

ISBN: (纸本)9781424472369

In this paper, we explore a parallel block multigrid preconditioner based on factorization of the coefficient matrix generated in three-dimensional unstructured grids system. This preconditioner is robust with respect to the magnitude of the mesh size and the coefficient complexity, apply smoothed aggregation algebraic multigrid which using block lower-upper symmetric Gauss-Seidel(BLU-SGS) as smoother to accelerate convergent rate. We focus on this method to three-dimensional, unstructured, large-scale, parallel and NS equations' steady-state simulations. The numerical results which conducted on NACA0012 airfoil indicate that nearly optimal convergence rates and computational complexity for parallel solutions, this method also provide high speedup and efficiency for a series of processors. © 2010 IEEE.

关键词： Navier Stokes equations

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nSET: Novel Simulation Method for Single-Electron Tunnel Device with 1-Dimension Multiple Islands

nSET: Novel Simulation Method for Single-Electron Tunnel Dev...

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3rd IEEE International NanoElectronics Conference (INEC)/Symposium on Nanoscience and Nanotechnology in China

作者： Sui, Bingcai Chi, Yaqing Fang, Liang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan 410073 China National University of Defense Technology China

ISBN: (纸本)9781424435432

Single-electronic transistors (SETs) are considered as the attractive candidates for post-COMS VLSI due to their ultra-small size and low power consumption. Because SETs with single island can not work at room temperature normally, more and more researchers begin to make research on the SETs with 1-dimension multi-islands. A new simulation method-nSET, is introduced in this paper Compared with other methods, nSET can simulate the SET device with 1-Dimension multiple islands with high speed and accuracy. Through the comparison, it can be get that nSET is accurate and fast compared with the classical Monte Carlo(MC) simulator, and is very useful for the ASIC design of SET devices.

关键词： Monte Carlo simulation single-electron tunneling device single-electron transistor multiple islands

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Software prepromotion for non-uniform cache architecture

Journal of Software

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Journal of Software 2010年第1期5卷 11-19页

作者： Wu, Junjie Pan, Xiaohui Yang, Xuejun National laboratory for parallel and distributed processing Changsha China

As a solution to growing global wire delay, non-uniform cache architecture (NUCA) has already been a trend in large cache designs. The access time of NUCA is determined by the distance between the cache bank containing the required data and the processor. Thus, one of the important NUCA researches focuses on how to place data to be used into cache banks close to the processor. This paper proposes software prepromotion technique, which prepromote data using prepromotion instructions as similar as software prefetching does. Besides the basic software prepromotion, this paper also proposes smart multihop software prepromotion (SMSP), very long software prepromotion (VLSP) and their combination technique. SMSP intelligently chooses cache banks which the prepromoted data most ideally suit to being moved into. And VLSP prepromote multiple data using one instruction. Finally, we evaluate our approaches by testing 7 kernel benchmarks on a full-system simulator. The basic software prepromotion gets an average improvement of 2.6893% in IPC. The SMSP improves IPC by 7.0928% averagely. And the VLSP gets an IPC improvement of 7.2194% averagely. Lastly, after combining the SMSP and VLSP, the average improvement in IPC achieves 11.8650%. © 2010 ACADEMY PUBLISHER.

关键词： Artificial intelligence

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Experimental results on algorithms for multiple keyword matching

Experimental results on algorithms for multiple keyword matc...

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作者： Kouzinopoulos, Charalampos S. Margaritis, Konstantinos G. Parallel and Distributed Processing Laboratory Department of Applied Informatics University of Macedonia 156 Egnatia Str. 54006 Thessaloniki Greece

ISBN: (纸本)9789728939199

Multiple keyword matching is a basic problem in computer science and is used to locate all the appearances of a finite set of keywords (the so called "patterns") inside an input string (the so called "text"). This paper presents experimental results for the well known Commentz-Walter, Wu-Manber, Set Backward Oracle Matching and Salmela-Tarhio-Kytöjoki multiple keyword matching algorithms. The algorithms are compared in terms of running time for random texts using a binary alphabet and texts using the English alphabet while the experimental results are validated against the theoretical complexity. © 2010 IADIS.

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High performance and memory efficient implementation of matrix multiplication on FPGAs

High performance and memory efficient implementation of matr...

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2010 International Conference on Field-Programmable Technology, FPT'10

作者： Wu, Guiming Dou, Yong Wang, Miao National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China Jiangnan Institute of Computing Technology Wuxi 214083 China

ISBN: (纸本)9781424489817

We present a high performance and memory efficient hardware implementation of matrix multiplication for dense matrices of any size on the FPGA devices. By applying a series of transformations and optimizations on the original serial algorithm, we can obtain an I/O and memory optimized block algorithm for matrix multiplication on FPGAs. A linear array of processing elements (PEs) is proposed to implement this block algorithm. We show significant reduction in hardware resources consuming compared to the related work while increasing clock frequency. Moreover, the memory requirement can be reduced to O(S) from O(S 2), where S is the block size. Therefore, more PEs can be integrated into the same FPGA devices. © 2010 IEEE.

关键词： Field programmable gate arrays (FPGA)

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