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IEEE International Nanoelectronics Conference (INEC)

作者： Bingcai Sui Yaqing Chi Liang Fang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan China National University of Defense Technology China

ISBN: (纸本)9781424435432

Single-electronic transistors (SETs) are considered as the attractive candidates for post-CMOS VLSI due to their ultra-small size and low power consumption. Because SETs with single island can not work at room temperature normally, more and more researchers begin to make research on the SETs with 1-dimension multi-islands. A new simulation method-nSET, is introduced in this paper. Compared with other methods, nSET can simulate the SET device with 1-dimension multiple islands with high speed and accuracy. Through the comparison, it can be get that nSET is accurate and fast compared with the classical Monte Carlo (MC) simulator, and is very useful for the ASIC design of SET devices.

关键词： Tunneling Programming profession Capacitance Circuit simulation Electrostatics Single electron transistors Application specific integrated circuits Discrete event simulation Very large scale integration Energy consumption

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Versatile Stack Management for Multitasking Sensor Networks

Versatile Stack Management for Multitasking Sensor Networks

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IEEE International Conference on distributed Computing Systems

作者： Rui Chu Lin Gu Yunhao Liu Mo Li Xicheng Lu National Laboratory for Parallel and Distributed Processing National University of Defense Technology Department of Computer Science and Engineering Hong Kong University of Science and Technology

ISBN: (纸本)9781424472611;9780769540597

The networked application environment has motivated the development of multitasking operating systems for sensor networks and other low-power electronic devices, but their multitasking capability is severely limited because traditional stack management techniques perform poorly on small-memory systems. In this paper, we show that combining binary translation and a new kernel runtime can lead to efficient OS designs on resource-constrained platforms. We introduce SenSmart, a multitasking OS for sensor networks, and present new OS design techniques for supporting preemptive multi-task scheduling, memory isolation, and versatile stack management. We have implemented SenSmart on MICA2/MICAz motes. Evaluation shows that SenSmart performs efficient binary translation and demonstrates a significantly better capability in managing concurrent tasks than other sensornet operating systems.

关键词： parallel processing (COMPUTERS) Sensor networks Electron devices Furnace conveyors Cache Memory System Operating systems osmium

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Blocking LU Decomposition for FPGAs

Blocking LU Decomposition for FPGAs

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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Guiming Wu Yong Dou Gregory D. Peterson National Laboratory for Parallel & Distributed Processing National University of Defense Technology Changsha China Electrical Engineering and Computer Science University of Tennessee Knoxville TN USA

To efficiently perform large matrix LU decomposition on FPGAs with limited local memory, the original algorithm needs to be blocked. In this paper, we propose a block LU decomposition algorithm for FPGAs, which is applicable for matrices of arbitrary size. We introduce a high performance hardware design, which mainly consists of a linear array of processing elements (PEs), to implement our block LU decomposition algorithm. A total of 36 PEs can be integrated into a Xilinx Virtex-5 xc5vlx330 FPGA on our self-designed PCI-Express card, reaching a sustained performance of 8.50 GFLOPS at 133 MHz, which outperforms previous work.

关键词： Field programmable gate arrays Matrix decomposition Hardware Power engineering computing Algorithm design and analysis Linear algebra Computer applications Concurrent computing distributed computing Laboratories

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Implementation of encrypted data for outsourced database

Implementation of encrypted data for outsourced database

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International Conference on Computational Intelligence and Natural Computing, CINC

作者： Zheng-Fei Wang Ai-Guo Tang National Key Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China Department of Computer Hunan Business College Changsha China

ISBN: (纸本)9781424477050

Encryption technology has become an important mechanism of securing data stored in the outsourced database. However, it is a difficulty to query efficiently the encrypted data and many researchers take it into consideration. To solve the problem, an encrypted schema, based on the Postgresql DBMS, is proposed. Through the security dictionary and the extended SQL, the approach implements the encrypted storage and efficiently query over the encrypted data in the outsourced databases. Results of experiments validate the efficiency and feasibility of our approach.

关键词： Indexes Dictionaries Random access memory Catalogs Encryption

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A Simulated Annealing Technique for Optimizing Time Warp Simulation

A Simulated Annealing Technique for Optimizing Time Warp Sim...

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International Conference on Computer Modeling and Simulation, ICCMS

作者： Wei Zhang Sina Meraji Jun Wang Carl Tropper National Laboratory of Parallel and Distributed Processing School of Computer Science National University of Defense Technology ChangSha China School of Computer Science McGill University Montreal Canada

According to Moore's law the complexity of VLSI circuits has doubled approximately every two years, resulting in simulation becoming the major bottleneck in the circuit design process. parallel and distributed simulations can be applied as fast, cost effective approaches to the simulation of large, complex circuits. In this paper, a simple yet effective simulated annealing-based approach is proposed to optimize the choice of a time window for optimistic parallel simulation. We chose gate level circuits simulations as our experimental vehicle. Our results show up to a 52% improvement in the simulation time using our simulated annealing algorithm. To the best of our knowledge, this is the first time that SA has been applied to optimize the performance of time warp simulations.

关键词： Time warp simulation Simulated annealing Circuit simulation Computational modeling Hardware design languages Discrete event simulation Computer simulation Voltage control Concurrent computing Computer science

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A compact model for multi-island single electron transistors

A compact model for multi-island single electron transistors

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IEEE International Nanoelectronics Conference (INEC)

作者： Yaqing Chi Haiqin Zhong Chao Zhang Liang Fang National Key Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan China National University of Defense Technology Changsha Hunan CN

Multi-island single electron transistor (MISET) is a kind of single electron transistor (SET), which has advantages of the room temperature operating. A novel semi-empirical compact model for MISET is proposed. The new approach combines the orthodox theory of single electron tunneling for single Coulomb island and a novel empirical analysis for a chain of Coulomb islands. The model is verified by the Monte-Carlo method in SIMON simulator, and is much faster than the traditional multi-island SET simulator, which has the advantages for the large scale multi-island SET circuit simulation.

关键词： Single electron transistors Circuit simulation Tunneling Large-scale systems Voltage Temperature Character generation Electrodes distributed processing Concurrent computing

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Effect of quantum capacitance on switching speed in T-CNFETs

Effect of quantum capacitance on switching speed in T-CNFETs

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IEEE International Nanoelectronics Conference (INEC)

作者： Hailiang Zhou Minxuan Zhang Yue Hao National Laboratory of Parallel and Distributed processing School of Computer National University of Defense Technology Changsha Hunan China School of Microelectronics Xidian University Xi'an Shanxi China

ISBN: (纸本)9781424435432;9781424435449

The effect of quantum capacitance (QC) on the switching speed in T-CNFETs (Tunneling Carbon Nanotube Field Effect Transistors) is investigated with simulation using NEGF (Non-Equilibrium Green's Function) formalism. Firstly, based on the analytical expression of SS, a quantitative study of the source/drain leads doping level is made to obtain an averaged inverse subthreshold slope(SS) as small as possible. And then the impact of QC on the gate control, thus on SS, is studied. Lastly, for the first time, approaches for restricting the impacts of QC are investigated, such as tuning the drain-source bias condition or CNT diameter which are governed by the analytical expression presented at the end of this paper. The modeling results reveal that the QC in T-CNFET has a negative impact on both the SS and on-current, and such impact could be restricted effectively with a proper choice of drain-source voltage and CNT chirality.

关键词： Quantum capacitance Doping Voltage Semiconductor process modeling Electrons Tunneling CNTFETs Green's function methods Iron PIN photodiodes

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Reducing cache contention in a multi-core processor via a scheduler

Reducing cache contention in a multi-core processor via a sc...

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International Conference on Advanced Computer Theory and Engineering, ICACTE

作者： S.Kazem Shekofteh Hossein Deldari Maryam Baradaran Khalkhali Parallel and Distributed Processing Laboratory Department of Computer Engineering Ferdowsi University of Mashhad Mashhad Iran Department of Computer Engineering Mashhad Branch Islamic Azad University Mashhad Iran

Multi-core architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance. Well scheduling of running threads on these processors will result in achieving higher performance. Modern multi-core systems are designed to allow clusters of cores to share various hardware structures, such as last-level caches, memory controllers, and interconnections, as well as prefetching hardware. Without considering these shared resources, scheduling the threads will cause serious degradation in overall performance of the system. In this paper we propose a novel algorithm to schedule the threads that considers these potential contentions to keep away from. The simulation results showed that the proposed scheduler would avoid from lots of contentions between threads on various resources especially on shared caches.

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Demand-Driven Memory Leak Detection Based on Flow-and Context-Sensitive Pointer Analysis

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Journal of Computer Science & Technology 2009年第2期24卷 347-356页

作者：王戟马晓东董威徐厚峰刘万伟 National Laboratory for Parallel and Distributed Processing National University of Defense Technology

We present a demand-driven approach to memory leak detection algorithm based on flow- and context-sensitive pointer analysis. The detection algorithm firstly assumes the presence of a memory leak at some program point and then runs a backward analysis to see if this assumption can be disproved. Our algorithm computes the memory abstraction of programs based on points-to graph resulting from flow- and context-sensitive pointer analysis. We have implemented the algorithm in the SUIF2 compiler infrastructure and used the implementation to analyze a set of C benchmark programs. The experimental results show that the approach has better precision with satisfied scalability as expected.

关键词： flow-sensitive memory leak detection demand-driven static analysis

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Reuse-aware modulo scheduling for stream processors 10

Reuse-aware modulo scheduling for stream processors

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Design, Automation and Test in Europe Conference and Exhibition

作者： Li Wang Jingling Xue Xuejun Yang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology China Programing Languages & Compilers Group School of Computer Science and Engineering University of New South Wales Australia

ISBN: (纸本)9783981080162

This paper presents reuse-aware modulo scheduling to maximizing stream reuse and improving concurrency for stream-level loops running on stream processors. The novelty lies in the development of a new representation for an unrolled and software-pipelined stream-level loop using a set of reuse equations, resulting in simultaneous optimization of two performance objectives for the loop, reuse and concurrency, in a unified framework. We have implemented this work in the compiler developed for our 64-bit FT64 stream processor. Our experimental results obtained on FT64 and by simulation using nine representative stream applications demonstrate the effectiveness of the proposed approach.

关键词： Processor scheduling Concurrent computing Streaming media Kernel Delay Equations Pipeline processing Laboratories Program processors distributed processing

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