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Journal of Software 2009年第3期4卷 240-246页

作者： Lu, Pingjing Che, Yonggang Wang, Zhenghua National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

The performance gap for high performance applications has been widening over time. High level program transformations are critical to improve applications' performance, many of which concern the determination of optimal values for transformation parameters, such as loop unrolling and blocking. Static approaches achieve these values based on analytical models that are hard to achieve because of increasing architecture complexity and code structures. Recent iterative compilation approaches achieve it by executing different versions of the program on actual platforms and select the one that renders best performance, outperforming static compilation approaches significantly. But the expensive compilation cost has limited their application scope to embedded applications and a small group of math kernels. This paper proposes a combinative approach--Combining Model and Iterative Compilation for Program Performance Optimization (CMIC). Such an approach first constructs a program optimization transformation model based on hardware performance counters to decide how and when to apply transformations, and then selects the optimal transformation parameters using Nelder-Mead simplex algorithm. Experimental results show that our approach can effectively improve programs' floating-point performance, reducing programs' runtime, therefore, lessening the performance gap for high-performance applications. © 2009 ACADEMY PUBLISHER.

关键词： Digital arithmetic

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FPGA accelerating three QR decomposition algorithms in the unified pipelined framework

FPGA accelerating three QR decomposition algorithms in the u...

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International Conference on Field Programmable Logic and Applications

作者： Yong Dou Jie Zhou Xiaoyang Chen Yuanwu Lei Jinbo Xu National Laboratory of Parallel & Distributed Processing National University of Defense Technology Changsha China

Many FPGA implementations for QR decomposition have been studied on small-scale matrix and all of them are presented individually. However to the best of our knowledge, there is no FPGA-based accelerator for large-scale QR decomposition. In this paper, we propose a unified FPGA accelerator structure for large-scale QR decomposition. To exploit the computational potential of FPGA, we introduce a fine-grained parallel algorithm for QR decomposition. A scalable linear array processing elements (PEs), which is the core component of the FPGA accelerator, is proposed to implement this algorithm. A total of 15 PEs can integrated into an Altera StratixII EP2S130F1020C5 on our self-designed board. Experimental results show that a factor of 4 speedup and the maximum powerperformance of 60.9 can be achieved compare to Pentium Dual CPU with double SSE thread.

关键词： Field programmable gate arrays Acceleration Pipelines Signal processing algorithms Large-scale systems Concurrent computing parallel algorithms Yarn Hardware Central processing Unit

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Transmission Scheduling in Data-Driven Peer-to-Peer Streaming towards Optimal Throughput

Transmission Scheduling in Data-Driven Peer-to-Peer Streamin...

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International Conference on Networking, Architecture, and Storage (NAS)

作者： Jiqing Wu Yuxing Peng Feng Liu National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

Peer-to-peer media streaming has been an important service on the internet in recent years. The Data-driven (or mesh-based) structure is adopted by most working systems,in which data scheduling is one of the important ***, those frequently used scheduling algorithms are often faced with such a case: A neighbor peer takes up its bandwidth to deliver the packets that other neighbors can also supply, but some packets only held by it are not *** packets can not be delivered in the current scheduling cycle, even though that the other neighbors have surplus bandwidth. This is a kind of waste of bandwidth and decreases the throughput of transmission. In this paper we propose anew scheduling algorithm aiming at the optimal throughput:Bipartite-matching based Block Scheduling algorithm(BBS).We convert the original data scheduling problem to a problem of finding a maximum match on the correspond bipartite graph, then assign data packets to neighbors according to the maximum match. We evaluate the performance of BBS with extensive experiments and the results show that BBS throughput and provides better streaming quality than those frequently used scheduling algorithms.

关键词： Peer to peer computing Throughput Bandwidth Scheduling algorithm Streaming media Laboratories distributed processing IP networks Web and internet services Bipartite graph

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Fault Tolerant parallel FFT Using parallel Failure Recovery

Fault Tolerant Parallel FFT Using Parallel Failure Recovery

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International Conference on Computational Science and its Applications (ICCSA)

作者： Hongyi Fu Xuejun Yang National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China

This paper introduces a new method based on parallel failure recovery, for the fault tolerance issue of parallel programs. In case a process fails, other surviving processes will compute the task of the failed one in parallel, so that the overhead for fault tolerance is leveled down. The paper presents the design and implementation of the parallel FFT using the new approach, and works on finding an optimum number of processes that participate in parallel failure recovery. Finally, an experiment is done to show the better performance of the parallel failure recovery over that of checkpointing, and to show the effectiveness of our solution for the best number of processes participating parallel failure recovery.

关键词： Fault tolerance Application software Grid computing Conferences Computer networks Physics computing Aerospace industry Computational geometry High performance computing Books

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Exploiting Fine-Grained Pipeline parallelism for Wavefront Computations on Multicore Platforms

Exploiting Fine-Grained Pipeline Parallelism for Wavefront C...

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International Conference on parallel processing Workshops (ICPPW)

作者： Guiming Wu Miao Wang Yong Dou Fei Xia National Laboratory for Parallel & Distributed Processing National University of Defense Technology Changsha China

This paper presents our experience with exploiting fine-grained pipeline parallelism for wavefront computations on a multicore platform. Wavefront computations have been widely applied in many application areas such as scientific computing algorithms and dynamic programming algorithms. To exploit fine-grained parallelism on multicore platforms, the programmers must consider the problems of synchronization, scheduling strategies and data locality. This paper shows the impact of fine-grained synchronization methods, scheduling strategies and data tile sizes on performance. We propose a low cost, lock-free, and lightweight synchronization method that can fully exploit pipeline parallelism. Our evaluation shows that RNAfold, an application for RNA secondary structures prediction, can achieve the best speedup of 3.88 on four cores under our framework.

关键词： Pipelines parallel processing Concurrent computing Multicore processing Heuristic algorithms Processor scheduling Scientific computing Dynamic programming Programming profession Tiles

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A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs

A Fine-grained Pipelined Implementation of the LINPACK Bench...

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Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM)

作者： Guiming Wu Yong Dou Yuanwu Lei Jie Zhou Miao Wang Jingfei Jiang National Laboratory of Parallel & Distributed Processing National University of Defense Technology Changsha China

Previous works have projected that the peak performance of FPGAs can outperform that of the general purpose processors. However, no work actually compares the performance between FPGAs and CPUs using the standard benchmarks such as the LINPACK benchmark. We propose and implement an FPGA-based hardware design of the LINPACK benchmark, the key step of which is LU decomposition with pivoting. We introduce a fine-grained pipelined LU decomposition algorithm that enables optimum performance by exploiting fine-grained pipeline parallelism. A scalable linear array of processing elements (PEs), which is the core component of our hardware design, is proposed to implement this algorithm. To the best of our knowledge, this is the first reported FPGA-based pipelined implementation of LU decomposition with pivoting. A total of 19 PEs can be integrated into an Altera Stratix II EP2S130F1020C5 on our self-designed development board. Experimental results show that the speedup up to 6.14 can be achieved relative to a Pentium 4 processor for the LINPACK benchmark.

关键词： Field programmable gate arrays Hardware Equations Algorithm design and analysis Concurrent computing distributed computing Laboratories distributed processing Pipelines parallel processing

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A Peer-to-Peer Media Streaming System Based on the iVCE Platform

A Peer-to-Peer Media Streaming System Based on the iVCE Plat...

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International Conference on parallel and distributed Systems (ICPADS)

作者： Jiqing Wu Yuxing Peng Rui Shen National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China

With the advancement of peer-to-peer technology, media streaming applications become more and more popular in the Internet. However, the traditional development methods for this kind of applications need developers not only to consider the application logic but also to manage the dynamics of Internet resources, thus increasing the difficulty of development and limiting the deployment of personal video distribution applications. In this paper, we design and implement a peer-to-peer streaming system in a much easier way. In this way we can concentrate on the application itself without distraction from the dynamics of Internet resources. Such simplification owes to the Internet-based Virtual Computing Environment (iVCE), which provides programming abstractions and runtime utilities that can encapsulate the complexity of managing transient resources into the platform, thus facilitating the construction of Internet applications. When we build our streaming application based on the iVCE, we only need to define the interaction protocols among distributed nodes with the Owlet programming language. Also, we implement a JavaBean, which can be used by the Owlet program, to assist the transferring and rendering of the content. Our implementation shows that peer-to-peer applications such as media streaming, can be elegantly built using the iVCE platform, and it can serve as a reference implementation for developing similar applications.

关键词： Streaming media Peer to peer computing Internet Resource management Logic Utility programs Runtime environment Environmental management Protocols Computer languages

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Matrix Inversion on the Cell/B.E. Processor

Matrix Inversion on the Cell/B.E. Processor

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IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Shodai Yokoyama Kazuya Matsumoto Stanislav Sedukhin Distributed Parallel Processing Laboratory Graduate School of Computer Science and Engineering University of Aizu Japan

The problem of inverting matrices is one that occurs in some problems of practical importance. This paper introduces and evaluates the block algorithm for high performance matrix inversion on the Cell Broadband Engine (Cell/B.E.) processor. The Cell/B.E. is a heterogeneous multi-core processor on a single-chip jointly developed by Sony, Toshiba and IBM, which has a very high speed of the single precision floating-point arithmetic. The discussed matrix inversion algorithm is a combination of the block algebraic path problem algorithm and the well-known block matrix inversion algorithm based on the LU decomposition. For relatively big matrices, this combined block algorithm spends the most time in computing matrix-matrix multiplication of blocks and achieves 149.4 Gflop/s on Cell/B.E., when PPE and six SPEs of PlayStation3 are used, or 93.4% of the aggregated double (PPE) and single (SPEs) precision peak performance, which is 160.0 Gflop/s.

关键词： Matrix decomposition Partitioning algorithms Floating-point arithmetic Engines Multicore processing Microprocessors Reduced instruction set computing High performance computing parallel processing Computer science

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A Two-Phase Mapping Method for parallel Applications Simulation

A Two-Phase Mapping Method for Parallel Applications Simulat...

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International Conference on Computational Intelligence and Software Engineering (CiSE)

作者： Jianbin Fang Chuanfu Xu Yonggang Che Yufen Weng Zhenghua Wang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

Efficient mapping of logical processes to physical processes is one of key technologies to accelerate parallel performance simulation. Aiming at minimizing the communications between SMP nodes and between host physical processes, this paper presents a novel method named TPsmp-LP 3 M. It automatically extracts communication pattern of logical processes from trace and then generates a two-phase mapping from logical processes to SMP clusters. Experimental results show that TPsmp-LP 3 M can outperform the regular mapping method by up to 20.2%.

关键词： Computational modeling Computer simulation Bandwidth Predictive models Discrete event simulation Concurrent computing parallel processing Application software Laboratories distributed processing

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Towards efficient mapping in large-scale trace-driven parallel performance simulation

Towards efficient mapping in large-scale trace-driven parall...

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IEEE Youth Conference on Information, Computing and Telecommunication, YC-ICT

作者： Chuanfu Xu Yonggang Che Jianbin Fang Zhenghua Wang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

In parallel performance simulation of parallel systems, a large amount of logic processes (LP) must be mapped to relatively small number of physical elements (PE). Previous researches have shown that different mapping schemes could result in significant variation in the whole parallel simulation cost. In this paper, we propose, implement, and evaluate a minimum communication-guided mapping (MiniCoM) scheme for large-scale trace-driven parallel performance simulation. Guided by extracted information about interactions among LPs from previously generated traces, MiniCoM can map some most frequently interacted LPs to the same PE while trying to keep load balance between PEs. The mapping aims to minimize realistic communications among PEs which may run on different nodes of host systems with large inter-node latency. We use BigSim simulator and two target programs to evaluate MiniCoM. Our results show that MiniCoM is more efficient than blocked mapping adopted by BigSim: it can reduce the total parallel simulation runtime by up to 49%.

关键词： Large-scale systems Computational modeling parallel processing Discrete event simulation Computer simulation Concurrent computing Data mining Laboratories distributed processing distributed computing

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