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Memory based processor array for artificial neural networks

Memory based processor array for artificial neural networks

引用

1997 IEEE International Conference on Neural Networks, ICNN 1997

作者： Kim, Youngsik Noh, Mi-Jung Han, Tack-Don Kim, Shin-Dug Yang, Sung-Bong Parallel Processing System Laboratory Dept. of Computer Science Yonsei University Seoul 120-749 Korea Republic of

ISBN: (纸本)0780341228

In this paper an effective memory-processor integrated architecture, called memory based processor array for artificial neural networks (MPAA), is proposed. The MPAA can be easily integrated into any host system via memory interface. Specifically, the MPAA system provides an efficient mechanism for its local memory accesses allowed by the row basis and the column basis using the hybrid row and column decoding, which is suitable for the computation model of ANNs such as the accessing and alignment patterns given for matrix-by-vector operations. Mapping algorithms to implement the multilayer perceptron with backpropagation learning on the MPAA system are also provided. The proposed algorithms support both neuron and layer level parallelisms which allow the MPAA system to operate the learning phase as well as the recall phase in the pipelined fashion. Performance evaluation is provided by detailed comparison in terms of two metrics such as the cost and the number of computation steps. © 1997 IEEE.

关键词： Neural networks

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An unsupervised deep learning framework for gene regulatory network inference from single-cell expression data

An unsupervised deep learning framework for gene regulatory ...

引用

2023 IEEE International Conference on Bioinformatics and Biomedicine, BIBM 2023

作者： Mao, Guo Liu, Jie National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory Changsha410073 China National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Laboratory of Software Engineering for Complex System Changsha410073 China

ISBN: (纸本)9798350337488

Recent advances in single-cell RNA sequencing (scRNA-seq) technology provides unprecedented opportunities for reconstruction gene regulation networks (GRNs). At present, many different models have been proposed to infer GRN from a large number of RNA-seq data, but most deep learning models use a priori gene regulatory network to infer potential GRNs. It is a challenge to reconstruct GRNs from scRNA-seq data due to the noise and sparsity introduced by the dropout effect. Here, we propose GAALink, a novel unsupervised deep learning method. It first constructs the gene similarity matrix and then refines it by threshold value. It then learns feature representations of genes through a graphical attention autoencoder that propagates information across genes with different weights. Finally, we use gene feature expression for matrix completion such that the GRNs are reconstructed. Compared with seven existing GRNs reconstruction methods, GAALink achieves more accurate performance on seven scRNA-seq dataset with four ground truth networks. GAALink can provide a useful tool for inferring GRNs for scRNA-seq expression data. © 2023 IEEE.

关键词： Feature representations Gene similarity matrix Graphical attention autoencoder Matrix completion Unsupervised deep learning method

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A selective compressed memory system by on-line data decompressing

A selective compressed memory system by on-line data decompr...

引用

25th EUROMICRO Conference on Informatics: Theory and Practice for the New Millennium, EUROMICRO 1999

作者： Lee, Jang-Soo Hong, Won-Kee Kim, Shin-Dug Parallel Processing System Laboratory Department of Computer Science Yonsei University 134 Shinchon-Dong Seodaemun-Ku Seoul 120-749 Korea Republic of

ISBN: (纸本)0769503217

The article proposes a selective compressed memory system (SCMS) focusing on a compressed cache architecture, in which only data blocks with good compression efficiency are compressed selectively and all compressed blocks are stored in a fixed memory space. The selective compression technique can reduce decompression overhead caused by online data decompression and also the fixed memory space allocation allows efficient management of the compressed blocks. The results from a trace driven simulation show that the SCMS approach can provide around a 35% decrease in the on-chip cache miss ratio as well as a 53% decrease in the data traffic over conventional memory systems. Furthermore, a large amount of the decompression overhead can be reduced, and thus the average memory access time can also be reduced by a maximum 20% against conventional memory systems. © 1999 IEEE.

关键词： Cost reduction

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A continuous stream service and high service availability mechanism for continuous media servers

A continuous stream service and high service availability me...

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6th International Conference on Advanced Communication Technology: Broadband Convergence Network Infrastructure

作者： Jung, Sung-In Lee, Cheol-Hoon Computer System Division Electron./Telecom. Res. Institute Daejon Korea Republic of Parallel Processing Laboratory Department of Computer Engineering Chungnam National University Daejon Korea Republic of

ISBN: (纸本)8955191197

Due to the explosive growth of the Internet, stream services are becoming more popular. The large media servers supporting thousands of concurrent media streams have to satisfy us with both good throughout and high availability. Although they are reciprocal from the viewpoint of system performance, the stream service continuity, as well as throughput, should be considered in clustered media servers. This is because media stream services should be continuously available to the clients even on the event of system failure. In this paper, we introduce service availability as the gauge of service degree on media servers, and present the basic scheme for guaranteeing continuous stream service. To do this, we propose LSS(Log Stream Status) and RRD(Ready Resource for instant Delivery) mechanisms. They are classified according to the status management method of stream service and the resumption method of closed service. Although these mechanisms require additional overhead, we found that they can be applied to clustered media servers with minimum overhead. Additionally, we concluded that they can provide higher quality of service availability on traditional clustered media servers.

关键词： Servers

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An improved lookahead instruction prefetching

An improved lookahead instruction prefetching

引用

International Conference on High Performance Computing in the Asia-Pacific Region

作者： Gi-Ho Park Oh-Young Kwon Tack-Don Han Shin-Dug Kim Sung-Bong Yang Parallel Processing System Laboratory Department of Computer Science Yonsei University Seoul South Korea

A new lookahead instruction prefetching mechanism is proposed in this paper. Though significant performance improvement can be obtained by improving both the cache miss ratio and average access time for successfully prefetched blocks, most conventional prefetching mechanisms improve only one out of the two factors. To achieve balanced improvement of the two factors, a lookahead prefetching scheme that fetches multiple blocks for a prefetch request and adopts prefetch on miss mechanism is proposed. Performance evaluation is carried out through the trace-driven simulation and the proposed prefetch scheme reduces 32%/spl sim/56% of the memory access delay time of the cache system that does not perform any prefetching.

关键词： Prefetching Delay effects parallel processing Laboratories Computer science Performance evaluation Cache memory History Performance analysis Boolean functions

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An effective full-map directory scheme for the sectored caches

An effective full-map directory scheme for the sectored cach...

引用

International Conference on High Performance Computing in the Asia-Pacific Region

作者： Won-Kee Hong Tack-Don Han Shin-Dug Kim Sung-Bong Yang Parallel Processing System Laboratory Department of Computer Science Yonsei University Seoul South Korea

In multiprocessor systems, the cache misses due to coherence transactions make up many of the total cache misses. However this type of cache miss is strongly dependent on the type of data sharing among processors, especially false sharing. Until now the small cache block size has been used to avoid false sharing mainly in multiprocessor systems, but the smaller the cache block size, the lower the prefetching effect. Moreover it is shown that high spatial locality appears in many parallel programs. The paper presents two advanced full-map directory schemes which provide a low cache miss ratio and communication traffic by avoiding false sharing and taking advantage of the spatial locality existing in many parallel programs. The performance was evaluated by the event-driven simulator and the empirical results show that the proposed scheme can provide about a 6/spl sim/77% decrease in the cache miss ratio and a 46/spl sim/96% decrease in the communication traffic.

关键词： Multiprocessing systems Prefetching parallel processing Laboratories Computer science Discrete event simulation Delay Access protocols Memory management Performance evaluation

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A selective compressed memory system by on-line data decompressing

A selective compressed memory system by on-line data decompr...

引用

EUROMICRO Conference

作者： Jang-Soo Lee Won-Kee Hong Shin-Dug Kim Parallel Processing System Laboratory Department of Computer Science Yonsei University Seoul South Korea

关键词： Cache memory Bandwidth parallel processing Laboratories Computer science Memory management Hip Delay Process design Bridges

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Memory based processor array for artificial neural networks

Memory based processor array for artificial neural networks

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International Conference on Neural Networks

作者： Youngsik Kim Mi-Jung Noh Tack-Don Han Shin-Dug Kim Sung-Bong Yang Parallel Processing System Laboratory Department of Computer Science Yonsei University Seoul South Korea

ISBN: (纸本)0780341228

关键词： Artificial neural networks Computer architecture parallel processing Backpropagation algorithms Neurons Decoding Computational modeling Memory architecture Bandwidth Read-write memory

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Design and evaluation of a selective compressed memory system

Design and evaluation of a selective compressed memory syste...

引用

IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Jang-Soo Lee Won-Kee Hong Shin-Dug Kim Department of Computer Science Parallel Processing System Laboratory Yonsei University Seoul South Korea

This research explores any potential for an on-chip cache compression which can reduce not only cache miss ratio but also miss penalty, if main memory is also managed in compressed form. However, the decompression time causes a critical effect on the memory access time and variable-sized compressed blocks tend to increase the design complexity of the compressed cache architecture. This paper suggests several techniques to reduce the decompression overhead and to manage the compressed blocks efficiently which include selective compression, fixed space allocation for the compressed blocks, parallel decompression, the use of a decompression buffer, and so on. Moreover a simple compressed cache architecture based on the above techniques and its management method are proposed. The results from trace-driven simulation show that this approach can provide around 35% decrease in the on-chip cache miss ratio as well as a 53% decrease in the data traffic over the conventional memory systems. Also, a large amount of the decompression overhead can be reduced, and thus the average memory access time can also be reduced by maximum 20% against the conventional memory systems.

关键词： Memory management Delay Hip Bandwidth parallel processing Laboratories Computer science Ores Read only memory Process design

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Dynamic load balancing of iterative data parallel problems on a workstation cluster

Dynamic load balancing of iterative data parallel problems o...

引用

International Conference on High Performance Computing in the Asia-Pacific Region

作者： Hye-Seon Maeng Hyoun-Su Lee Tack-Don Han Sung-Bong Yang Shin-Dug Kim Parallel Processing System Laboratory Department of Computer Science Yonsei University Seoul South Korea

Dynamic load balancing of the workloads of clustered workstations has emerged as a powerful solution for overcoming load imbalance. In order to detect such imbalances, some load balancing methods check the average idle-time of the workstations periodically. But in these methods load balancing cannot be performed until the end of a period even if load imbalance has occurred in the middle of the period. In this paper, we present a new threshold load balancing method for workstations which process the jobs with relatively long execution times. The new method decides a proper time to perform load balancing and does perform the balancing right after the detection of the load imbalance. We also show that a static load balancing method with a long period is suitable if the workstations have to deal with the jobs having unpredictable arrival times and relatively short execution times. The performance of the methods presented in this paper is compared with the method without load balancing as well as with the periodic methods in (Siegell and Steenkiste, 1994), (Nedeljkovic and Quinn, 1992) and (Schnekenburger and Huber, 1994). The experiments were done with an iterative data parallel problem called the ISING problem (Saltz et al., 1995). The experimental results show that our methods outperform all the other methods that we compared.

关键词： Load management Workstations parallel processing Laboratories Computer science Runtime Exponential distribution

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