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2023 IEEE International Conference on Bioinformatics and Biomedicine, BIBM 2023

作者： Mao, Guo Liu, Jie National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory Changsha410073 China National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Laboratory of Software Engineering for Complex System Changsha410073 China

ISBN: (纸本)9798350337488

Recent advances in single-cell RNA sequencing (scRNA-seq) technology provides unprecedented opportunities for reconstruction gene regulation networks (GRNs). At present, many different models have been proposed to infer GRN from a large number of RNA-seq data, but most deep learning models use a priori gene regulatory network to infer potential GRNs. It is a challenge to reconstruct GRNs from scRNA-seq data due to the noise and sparsity introduced by the dropout effect. Here, we propose GAALink, a novel unsupervised deep learning method. It first constructs the gene similarity matrix and then refines it by threshold value. It then learns feature representations of genes through a graphical attention autoencoder that propagates information across genes with different weights. Finally, we use gene feature expression for matrix completion such that the GRNs are reconstructed. Compared with seven existing GRNs reconstruction methods, GAALink achieves more accurate performance on seven scRNA-seq dataset with four ground truth networks. GAALink can provide a useful tool for inferring GRNs for scRNA-seq expression data. © 2023 IEEE.

关键词： Feature representations Gene similarity matrix Graphical attention autoencoder Matrix completion Unsupervised deep learning method

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An unsupervised deep learning framework for gene regulatory network inference from single-cell expression data

An unsupervised deep learning framework for gene regulatory ...

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IEEE International Conference on Bioinformatics and Biomedicine (BIBM)

作者： Guo Mao Jie Liu Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China Laboratory of Software Engineering for Complex System National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

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Optimizing All-to-All Collective Communication on Tianhe Supercomputer

Optimizing All-to-All Collective Communication on Tianhe Sup...

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IEEE International Conference on Big Data and Cloud Computing (BdCloud)

作者： Jintao Peng Jie Liu Yi Dai Min Xie Chunye Gong National University of Defense Technology ChangSha China Science and Technology on Parallel and Distributed Processing Laboratory NUDT Changsha China Changsha and Laboratory of Software Engineering for Complex System NUDT Changsha China

All-to-all communication has a wide range of ap-plications in parallel applications like FFT. On most supercom-puters, there are multiple cores in a node. Message aggregation is an efficient method for smaller messages. Using multi-leader to aggregate message show significant improvement in intra-node overhead. However, compared to one-leader aggregation, existing multi-leader design incurs more message count and less aggregated message size. This paper proposes an Overlapped Multi-worker Multi-port all-to-all (OVALL) to scale the message size and parallelism of the aggregation algorithm. The algorithm exploits the all-to-all multi-core parallelism, concurrent commu-nication, and overlapping capabilities. Experiment results show that, compared to systems built-in MPI, OVALL'implementation achieves up to 5.9x or 18x speedup compared to MPI on different HPC systems. For the Fast Fourier Transform (FFT) application, OVALL is up to 2.7x (8192 cores, system A) or 5.6x (4800 cores, system B) faster compared to built-in MPI on peak performance.

关键词： Multicore processing Fast Fourier transforms Scalability Aggregates Supercomputers Libraries Pipeline processing

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A Retina-LGN-V1 Structure-like Spiking Neuron Network for Image Feature Extraction 21

A Retina-LGN-V1 Structure-like Spiking Neuron Network for Im...

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Proceedings of the 2021 5th International Conference on Video and Image processing

作者： Sheng Ji Qijun Gu Ye Yuan Peng Zhao Tao Fang Hong Huo Xin Niu Department of Automation_School of Electronic Information and Electrical Engineering_Key Laboratory of System Control and Information Processing Ministry of Education Shanghai Jiao Tong University China College of Computer Science and Technology on Parallel and Distributed Laboratory National University of Defense Technology China

ISBN: (纸本)9781450385893

SNNs have achieved great attention in recent years as they contain neurons more like those in the brain and use spikes to encode and transmit information efficiently among neurons with lower energy consumption. A Retina-LGN-V1 structure-like spiking neuron network (RLVSL-SNN) is proposed in this paper. It is inspired by the structure of mammalian primary visual pathway, and simulates different biological structures of Retina, LGN and V1. Noise reduction circuit and light adaptation circuit are also simulated for enhancing the robustness of its extracted features. RLVSL-SNN is a bio-plausible neuron network as it has firing rates of neurons in each layer that are similar to those of biological experiments. Besides, a full-connected SNN (FC SNN) is implemented following RLVSL-SNN for classification to evaluate the extracted features. The additive spiking timing dependent plasticity (STDP) learning rules and the ANN-to-SNN conversion method are utilized to train RLVSL-SNN and FC SNN, respectively. The experiments on MNIST dataset have verified that RLVSL-SNN is comparable to AlexNet for classification by features from spikes.

关键词： Additive Spiking Timing Dependent Plasticity Learning Primary Visual Pathway Image Classification Spiking Neural Network

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A Heterogeneous Processor Design for CNN-Based AI Applications on IoT Devices 8

A Heterogeneous Processor Design for CNN-Based AI Applicatio...

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8th International Conference on Identification, Information and Knowledge in the Internet of Things, IIKI 2019

作者： Liu, Zhiqiang Jiang, Jingfei Lei, Guoqing Chen, Kai Qin, Buyue Zhao, Xiaoqiang Artificial Intelligence Research Center National Innovation Institute of Defense Technology Beijing China National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China College of Computer National University of Defense Technology Changsha China College of System Engineering National University of Defense Technology Changsha China

This paper proposes a heterogeneous processor design for CNN-based AI applications on IoT devices. The heterogeneous processor contains an embedded RISC-V CPU that works as a general processor and an efficient CNN-accelerator that supports a variety of CNN models with a list of macro instructions. For demonstration, we implement a prototype on an FPGA platform with the RISC-V CPU working under 20 MHz and the CNN accelerator working under 100 MHz. As a case study, we run a CNN-based face detection and recognition application on this prototype. The prototype can process one image in 0.72 seconds and an ASIC implementation working under 400 MHz can process one image in less than 0.15 seconds by estimation, which can satisfy the needs for many IoT scenarios such as access control systems and check-in systems. © 2020 The Authors. Published by Elsevier B.V.

关键词： Internet of things

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Deep reinforcement learning for combinatorial optimization: Covering salesman problems

arXiv

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arXiv 2021年

作者： Li, Kaiwen Zhang, Tao Wang, Rui Wang, Yuheng Han, Yi College of Systems Engineering National University of Defense Technology Changsha410073 China Hunan Key Laboratory of Multi-Energy System Intelligent Interconnection Technology HKL-MSI2T Changsha410073 China Graduate College National University of Defense Technology Changsha410073 China Science and Technology on Parallel and Distributed Processing Laboratory College of Computer National University of Defense Technology Changsha410073 China

This paper introduces a new deep learning approach to approximately solve the Covering Salesman Problem (CSP). In this approach, given the city locations of a CSP as input, a deep neural network model is designed to directly output the solution. It is trained using the deep reinforcement learning without supervision. Specifically, in the model, we apply the Multi-head Attention to capture the structural patterns, and design a dynamic embedding to handle the dynamic patterns of the problem. Once the model is trained, it can generalize to various types of CSP tasks (different sizes and topologies) with no need of re-training. Through controlled experiments, the proposed approach shows desirable time complexity: it runs more than 20 times faster than the traditional heuristic solvers with a tiny gap of optimality. Moreover, it significantly outperforms the current state-of-the-art deep learning approaches for combinatorial optimization in the aspect of both training and inference. In comparison with traditional solvers, this approach is highly desirable for most of the challenging tasks in practice that are usually large-scale and require quick decisions. Copyright © 2021, The Authors. All rights reserved.

关键词： Combinatorial optimization

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A Heterogeneous Processor Design for CNN-Based AI Applications on IoT Devices

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Procedia Computer Science 2020年 174卷 2-8页

作者： Zhiqiang Liu Jingfei Jiang Guoqing Lei Kai Chen Buyue Qin Xiaoqiang Zhao Artificial Intelligence Research Center National Innovation Institute of Defense Technology Beijing China National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China College of Computer National University of Defense Technology Changsha China College of System Engineering National University of Defense Technology Changsha China

关键词： Processor RISC-V Accelerator AI (Artificial Intelligence) CNN (Convolutional Neural Network) IoT (Internet of Things)

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Maximizing Uniform Multicast Throughput in Multi-Channel Dense Wireless Sensor Networks 12

Maximizing Uniform Multicast Throughput in Multi-Channel Den...

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12th International Conference on Mobile Ad-Hoc and Sensor Networks, MSN 2016

作者： Jiao, Xianlong Chen, Guirong Wang, Xiaodong Chen, Yuli Yang, Li Information and Navigation College Air Force Engineering University Xi'an710077 China College of Information System and Management National University of Defense Technology Changsha410073 China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha410073 China Chongqing Guanyinqiao Elementary School Chongqing400020 China Chongqing Liangjiangxinqu Renhe Experimental School Chongqing400021 China

ISBN: (纸本)9781509056965

This paper investigates the problem of maximizing uniform multicast throughput (MUMT) for multi-channel dense wireless sensor networks, where all nodes locate within one-hop transmission range and can communicate with each other on multiple orthogonal channels. This kind of networks show wide application in the real world, and maximizing uniform multicast throughput for these networks is worth deep studying. Previous researches have proved MUMT problem is NP-hard. However, previous researches are either hard to implement, or use too many relay nodes to complete the multicast task, and thus incur high overhead or poor performance. To efficiently solve MUMT problem, we adopt the concept of the maximum independent set with the size constraint, and present one novel Single-Broadcast based Multicast algorithm called SBM based on the concept. We prove that SBM algorithm achieves a constant ratio to the theoretical throughput upper bound. Extensive experimental results demonstrate that, SBM performs better than existing work in terms of both the uniform multicast throughput and the total number of transmissions. © 2016 IEEE.

关键词： Throughput

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Maximizing Uniform Multicast Throughput in Multi-Channel Dense Wireless Sensor Networks

Maximizing Uniform Multicast Throughput in Multi-Channel Den...

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International Conference on Mobile Ad-hoc and Sensor Networks, MSN

作者： Xianlong Jiao Guirong Chen Xiaodong Wang Yuli Chen Li Yang College of Information System and Management National University of Defense Technology Changsha Information and Navigation College Air Force Engineering University Xi'an Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha Chongqing Guanyinqiao Elementary School Chongqing Chongqing Liangjiangxinqu Renhe Experimental School Chongqing

ISBN: (纸本)9781509056972

关键词： Throughput Wireless sensor networks Approximation algorithms Schedules Data communication Algorithm design and analysis Relays

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RPSim: A Rapid Prototyping Full-system Simulator for SoC Software Development

RPSim: A Rapid Prototyping Full-System Simulator for SoC Sof...

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International Conference on Networking, Architecture, and Storage (NAS)

作者： Haojun Wang Qinghao Min Yi Li Weihua Zhang Software School Fudan University Shanghai China Shanghai Key Laboratory of Data Science Fudan University Shanghai China State Key Laboratory of ASIC & System Fudan University Shanghai China Parallel Processing Institute Fudan University Shanghai China

Nowadays, the release of SoC products has come to a burst. Time-to-market of these products has been shortened to an extreme, nearly 8 to 12 months. To reduce production period, hardware architects generally combine well-tuned IP cores in their designs. To guarantee the process of SoC software development, which will finally decide the release time of products, a fast prototyping simulation platform for SoC software development should be available as soon as possible after hardware design. However, state-of-the-art SoC simulators lack the support for fast integration of IP core and require time-consuming compiler chain modifications for new instructions. In this paper, we present Prism, an extensible and easy-to-use full-system SoC simulation platform for SoC software development. Two mechanisms are designed and implemented to support fast prototyping for new IP core simulation or new instruction extension without compiler tool chain modifications. First, a hardware and software hybrid mechanism is proposed for IP core fast prototyping. A seamless interface is used to eliminate the differences among IP cores. Second, a configurable library mechanism is designed for new instruction extension. Register dependence can be maintained for detailed timing simulation without compiler tool chain modification. In such a design, the major effort for extension is to specify the elaborate common customization interface. Experimental results show these mechanisms only involve about 0.36% runtime overhead. Based on RPSim, a graduate student only needs write about 40 lines of code and takes less than half an hour to extend a new IP core simulation in RPSim.

关键词： IP networks Frequency modulation Field programmable gate arrays system-on-chip Timing Libraries Software

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