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2nd International Conference on Software Engineering and Data Mining, SEDM 2010

作者： Cao, Zining National Key Laboratory of Science and Technology on Avionics System Integration Shanghai 200233 China Department of Computer Science and Technology Nanjing University of Aero. and Astro. Nanjing 210016 China Provincial Key Laboratory for Computer Information Processing Technology Soochow University Suzhou 215006 China

ISBN: (纸本)9788988678213

In this paper, we first propose a specification approach combining interface automata and Z language. This approach can be used to describe temporal properties and data properties of software components. A branching time logic for ZIAs is presented. We then give an algorithm for model checking this logic on ZIAs with finite domain. Furthermore, we present a mu-calculus logic for ZIAs, and give a model checking algorithm for this logic.

关键词： Model checking

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Extending interface automata with Z notation

Extending interface automata with Z notation

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4th IPM International Conference on Fundamentals of Software Engineering, FSEN 2011

作者： Cao, Zining Wang, Hui National Key Laboratory of Science and Technology on Avionics System Integration Shanghai 200233 China Department of Computer Science and Technology Nanjing University of Aero. and Astro. Nanjing 210016 China Provincial Key Laboratory for Computer Information Processing Technology Soochow University Suzhou 215006 China

In this paper, we propose a specification approach combining interface automata and Z language. This approach can be used to describe behavioural properties and data properties of software components. We also study th... 详细信息

ISBN: (纸本)9783642293191

关键词： Automata theory

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A multi-layered emulation platform to verify the effectiveness of consistency control approaches about message ordering

A multi-layered emulation platform to verify the effectivene...

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IEEE International Conference on Communication Software and Networks

作者： Zhou, Hangjun Fu, Sha Department of Information Management Hunan University of Finance and Economics Chang Sha Hu Nan China Key Laboratory of Science and Technology for National Defence of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Chang Sha Hu Nan China

ISBN: (纸本)9781612844855

It is an important issue to preserve the consistent delivering order of messages at each site in Distributed Virtual Environments(DVEs). Currently, the violations of message delivery order are inclined to happen in the large-scale and frequently interactive DVEs running on Wide Area Network(WAN). The inconsistent anomalies are characterized as unpredictable, unrepeatable and uncontrollable, which results in the severe problem for the development of the consistency control approaches. Meanwhile, it is also highly expensive to directly verify the proposed approaches on WAN. Therefore, in this paper, we design and establish an original multi-layered emulation platform in LAN, which can emulate the network latency of WAN and repeat the scenarios of violations. On the platform, the designers of consistency approaches don't have to spend efforts to realize the fundamental functions of the verification, but could pay more attention to the development and optimization of the control algorithms, which is very beneficial for the improvement of message ordering approaches. © 2011 IEEE.

关键词： Wide area networks

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An efficient local address generation for the block-cyclic distribution

An efficient local address generation for the block-cyclic d...

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IEEE International Conference on Algorithms and Architectures for parallel processing (ICAP)

作者： Oh-Young Kwon Tae-Geun Kim Tack-Don Han Sung-Bong Yang Shin-Dug Kim Distributed Computing Laboratory Systems Engineering Research Institute Taejon South Korea Parallel Processing System Laboratory Department of Computer Science Yonsei University Seoul South Korea

ISBN: (纸本)0780342291

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time /spl Delta/M table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a /spl Delta/M table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time /spl Delta/M table generation method is faster than other algorithms in /spl Delta/M table generation time and access time for 10,000 array elements.

关键词： Runtime Equations Distributed computing systems engineering and theory parallel processing Laboratories computer science parallel languages Upper bound Automata

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Specification and identification of events for debugging and performance monitoring of distributed multiprocessor systems

Specification and identification of events for debugging and...

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International Conference on Distributed Computing systems

作者： J.E. Lumpp T.L. Casavant H.J. Siegel D.C. Marinescu Parallel Processing Laboratory Department of Electrical and Computer Engineering University of Iowa Iowa IA USA Parallel Processing Laboratory School of Electrical Engineering Purdue University USA Parallel Processing Laboratory School of Electrical Engineering Purdue University West Lafayette IN USA Computer Science Department Purdue University West Lafayette IN USA

The design of a debugging and performance analysis system that includes a specification language for process-level events and hardware for nonintrusive identification of these events during the execution of parallel and distributed application for a nonshared memory system is presented. The design is based on a formal event/action model and a layered architecture model that have been previously presented. Background, related work, and specification, and identification of events are discussed.< >

关键词： Debugging computerized monitoring Programming profession Multiprocessing systems parallel processing Laboratories Condition monitoring Hardware Application software Data structures

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Balance Multi-Head Attention based on Software and Hardware Co-design 9

Balance Multi-Head Attention based on Software and Hardware ...

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9th IEEE International Conference on Cyber Security and Cloud Computing and 8th IEEE International Conference on Edge Computing and Scalable Cloud, CSCloud-EdgeCom 2022

作者： Xu, Dian Hu, Wei Liu, Fang Fan, Zimeng Shi, Qingsong Wuhan University of Science and Technology Hubei Province Key Laboratory of Intelligent Information Processing and Real-time Industrial System College of Computer Science Wuhan China Wuhan University Department of Information Engineering Wuhan Institute of City School of Computer Science Wuhan China Zhejiang University College of Computer Science Hangzhou China

ISBN: (数字)9781665480666

ISBN: (纸本)9781665480666

Recently, the Transformer-based models have achieved leading results in many research areas such as natural language processing and computer vision. However, since Transformer-based models have a huge computational complexities, optimization for Transformer is the focus of current research. the core of Transformer models is the attention module, and in this paper we propose a software and hardware co-designed attention module, which reduces the computational units of the multi-head attention module by balancing the The inference time of the attention module is reduced by balancing the computational units of multiple attention modules. At the same time, we design the corresponding structure on FPGA, which accelerate 14.6x inference time in comparison with the original attention module implementation on GPU. We applied this attention module to multiple visual Transformer models and tested the accuracy difference between the balanced multi-head attention module-based model and the original model on CIFAR-10, and obtained a result of 80.46%, which lower from the original version by 0.18%. © 2022 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Hardware support for the Seamless programming model

Hardware support for the Seamless programming model

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Frontiers of Massively parallel Computation

作者： S.A. Fineberg T.L. Casavant B.H. Pease Computer Science Corporation USA Parallel Processing Laboratory Department of Electrical and Computer Engineering University of Iowa Iowa IA USA

The communication latency problem is presented with special emphasis on RISC (reduced instruction set computer) based multiprocessors. An interprocessor communication model for parallel programs based on locality is presented. This model enables the programmer to manipulate locality at the language level and to take advantage of currently available system hardware to reduce latency. A hardware node architecture for a latency-tolerant RISC-based multiprocessor, called Seamless, that supports this model, is presented. The Seamless architecture includes the addition of a hardware locality manager to each processing element, as well as an integral runtime environment and compiler.< >

关键词： Hardware Delay Yarn parallel processing Reduced instruction set computing Costs Coprocessors Communication system control parallel architectures Synchronization

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Static program decomposition among machines in an SIMD/SPMD heterogeneous environment with non-constant mode switching costs

Static program decomposition among machines in an SIMD/SPMD ...

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1995 Heterogeneous Computing Workshop, HCW 1994

作者： Watson, Daniel W. Antonio, John K. Siegel, Howard Jay Atallah, Mikhail J. Department of Computer Science Utah State University LoganUT84321-4205 United States Parallel Processing Laboratory School of Electrical Engineering Purdue University West LafayetteIN47907-1285 United States Computer Sciences Department Purdue University West LafayetteIN47907-1398 United States

ISBN: (纸本)0818655925

The problem of minimizing the execution time of programs within a heterogeneous environment is considered. Different computational characteristics within a parallel algorithm may make switching execution from one machine to another beneficial;however, the cost of switching between machines during the execution of a program must be considered. This cost is not constant, but depends on data transfers needed as a result of the move. Therefore, determining a minimum-cost assignment of machines to program segments is not straightforward. A previously presented Block-Based Mode Selection (BBMS) approach is used as a basis to develop a heuristic method for assigning machines to program segments of data-parallel algorithms. Simulation results of parallel program behavior using the heuristic indicate that good assignments are possible without resorting to exhaustive search techniques. © 1994 IEEE.

关键词： Heuristic methods

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A distributed management scheme for partitionable parallel computers

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IEEE Transactions on parallel and Distributed systems 1990年第1期1卷 120-126页

作者： M. Jeng H.J. Siegel Computer Science Department University of Houston Houston TX USA Parallel Processing Laboratory School of Electrical Engineering Purdue University West Lafayette IN USA

A distributed scheme for dynamic partitioning is investigated. Distributed procedures to split a subsystem and to combine subsystems are presented. The correctness of each of these two procedures is shown, and the complexity is analyzed. The procedures are applicable to parallel computers that use interconnection networks, such as hypercube, omega, multistage cube, and extra-stage cube networks.< >

关键词： Concurrent computing Distributed computing Multiprocessor interconnection networks computer networks parallel processing Application software Hypercubes Intelligent networks Resource management Large-scale systems

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Approach for automatic construction of ontology based on medication guide

Approach for automatic construction of ontology based on med...

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7th Chinese Semantic Web Symposium and the 2nd Chinese Web scienceConference, CSWS 2013

作者： Lu, Yuting Gu, Jinguang Huang, Zhisheng Computer Science and Technology Wuhan University of Science and Technology Wuhan 430065 China Hubei Province Key Laboratory of Intelligent Information Processing and Real-time Industrial System Wuhan 430065 China Department of Computer Science Vrije University of Amsterdam 1081hv Amsterdam Netherlands

ISBN: (纸本)9783642540240

Medication guide ontology has great significance for semantic study of rational use of drugs. Nowadays, medical ontology is mainly constructed manually, which spends a lot in time and manpower, and is also difficult to ensure the accuracy. This paper proposes a method of constructing the domain ontology of medication guide automatically. The method uses semantic pattern analysis to extract information, optimizes the extracted concepts and relations, generates medication guide ontology, and then provides the interface of pattern expansion to adapt to the changing medication guide data. Finally, it realizes the automatic construction of ontology system, and conducts experiments on to verify the feasibility of the system. © Springer-Verlag Berlin Heidelberg 2013.

关键词： Ontology

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