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"Cool" Load Balancing for High Performance Computing Data Centers

IEEE TRANSACTIONS ON COMPUTERS 2012年第12期61卷 1752-1764页

作者： Sarood, Osman Miller, Phil Totoni, Ehsan Kale, Laxmikant V. Univ Illinois Dept Comp Sci Parallel Programming Lab Urbana IL 61801 USA

As we move to exascale machines, both peak power demand and total energy consumption have become prominent challenges. A significant portion of that power and energy consumption is devoted to cooling, which we strive to minimize in this work. We propose a scheme based on a combination of limiting processor temperatures using dynamic voltage and frequency scaling (DVFS) and frequency-aware load balancing that reduces cooling energy consumption and prevents hot spot formation. Our approach is particularly designed for parallel applications, which are typically tightly coupled, and tries to minimize the timing penalty associated with temperature control. This paper describes results from experiments using five different CHARM++ and MPI applications with a range of power and utilization profiles. They were run on a 32-node (128-core) cluster with a dedicated air conditioning unit. The scheme is assessed based on three metrics: the ability to control processors' temperature and hence avoid hot spots, minimization of timing penalty, and cooling energy savings. Our results show cooling energy savings of up to 63 percent, with a timing penalty of only 2-23 percent.

关键词： Green IT temperature aware load balancing cooling energy DVFS

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PartialRC: A Partial Recomputing Method for Efficient Fault Recovery on GPGPUs

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Journal of Computer Science & Technology 2012年第2期27卷 240-255页

作者：徐新海杨学军薛京灵林宇斐林一松 National Laboratory for Parallel and Distributed Processing School of ComputerNational University of Defense Technology Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales

GPGPUs are increasingly being used to as performance accelerators for HPC （High Performance Computing） applications in CPU/GPU heterogeneous computing systems, including TianHe-1A, the world＇s fastest supercomputer in the TOP500 list, built at NUDT （National University of Defense Technology） last year. However, despite their performance advantages, GPGPUs do not provide built-in fault-tolerant mechanisms to offer reliability guarantees required by many HPC applications. By analyzing the SIMT （single-instruction, multiple-thread） characteristics of programs running on GPGPUs, we have developed PartialRC, a new checkpoint-based compiler-directed partial recomputing method, for achieving efficient fault recovery by leveraging the phenomenal computing power of GPGPUs. In this paper, we introduce our PartialRC method that recovers from errors detected in a code region by partially re-computing the region, describe a checkpoint-based faulttolerance framework developed on PartialRC, and discuss an implementation on the CUDA platform. Validation using a range of representative CUDA programs on NVIDIA GPGPUs against FullRC （a traditional full-recomputing Checkpoint-Rollback-Restart fault recovery method for CPUs） shows that PartialRC reduces significantly the fault recovery overheads incurred by FullRC, by 73.5% when errors occur earlier during execution and 74.6% when errors occur later on average. In addition, PartialRC also reduces error detection overheads incurred by FullRC during fault recovery while incurring negligible performance overheads when no fault happens.

关键词： GPGPU partial recomputing fault tolerance CUDA checkpointing

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Scalable detection of MPI-2 remote memory access inefficiency patterns

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INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2012年第3期26卷 227-236页

作者： Hermanns, Marc-Andre Geimer, Markus Mohr, Bernd Wolf, Felix German Res Sch Simulat Sci GmbH Lab Parallel Programming D-52425 Julich Germany Forschungszentrum Julich Julich Supercomp Ctr D-52425 Julich Germany Rhein Westfal TH Aachen Dept Comp Sci Aachen Germany

Wait states in parallel applications can be identified by scanning event traces for characteristic patterns. In our earlier work we defined such inefficiency patterns for MPI-2 one-sided communication, although still based on a serial trace-analysis scheme with limited scalability. In this article we show how wait states in one-sided communications can be detected in a more scalable fashion by taking advantage of a new scalable trace-analysis approach based on a parallel replay, which was originally developed for MPI-1 point-to-point and collective communication. Moreover, we demonstrate the scalability of our method and its usefulness for the optimization cycle with applications running on up to 32,768 cores.

关键词： MPI-2 pattern search performance analysis remote memory access scalability

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Scalable detection of MPI-2 remote memory access inefficiency patterns

Scalable detection of MPI-2 remote memory access inefficienc...

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作者： Hermanns, Marc-André Geimer, Markus Mohr, Bernd Wolf, Felix Laboratory for Parallel Programming German Research School for Simulation Sciences GmbH 52425 Jülich Germany Forschungszentrum Jülich Jülich Supercomputing Centre Germany Department of Computer Science RWTH Aachen University Germany

关键词： Scalability

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Dynamic Load Balancing for Unstructured Meshes on Space-Filling Curves

Dynamic Load Balancing for Unstructured Meshes on Space-Fill...

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IEEE International Symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Daniel F. Harlacher Harald Klimach Sabine Roller Christian Siebert Felix Wolf Applied Supercomputing in Engineering German Research School for Simulation Sciences GmbH RWTH University Aachen Germany Parallel Programming RWTH University Aachen Germany

ISBN: (纸本)9781467309745

Load imbalance is an important impediment on the path towards higher degrees of parallelism - especially for engineering codes with their highly unstructured problem domains. In particular, when load conditions change dynamically, efficient mesh partitioning becomes an indispensable ingredient of scalable design. However, popular graph-based methods such as those used by ParMetis require global knowledge, which effectively limits the problem size on distributed-memory machines. On such architectures, space-filling curves (SFCs) offer a memory-efficient alternative and many sophisticated schemes have already been proposed. In this paper, we present a simple strategy based on SFCs that is custom-tailored to the needs of static meshes with dynamically changing computational load. Exploiting the properties of this class of problems, it is not only easy to implement but also reduces memory requirements substantially. Moreover, exclusively relying on MPI collective operations, our load-balancing scheme also offers portable performance across a broad range of HPC systems. Experimental evaluation shows excellent scaling behavior for up to 16,384 cores on a Nehalem-Infiniband system and up to 294,912 processes on a Blue Gene/P system.

关键词： Memory management Partitioning algorithms Load modeling Load management Scalability Computational modeling Heuristic algorithms

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A dynamic accelerator-cluster architecture

A dynamic accelerator-cluster architecture

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41st International Conference on parallel Processing Workshops, ICPPW 2012

作者： Rinke, Sebastian Becker, Daniel Lippert, Thomas Prabhakaran, Suraj Westphal, Lidia Wolf, Felix Laboratory for Parallel Programming German Research School for Simulation Sciences 52062 Aachen Germany Department of Computer Science RWTH Aachen University 52062 Aachen Germany Corporate Technology Siemens AG 81739 München Germany Jülich Supercomputing Centre 52428 Jülich Germany MAGMA Giessereitechnologie GmbH 52072 Aachen Germany

ISBN: (纸本)9780769547954

Accelerators such as graphics processing units (GPUs) provide an inexpensive way of improving the performance of cluster systems. In such an arrangement, the individual nodes of the cluster are directly connected to one or more accelerator devices via PCI Express. This results in a static mapping of accelerators onto compute nodes, where each accelerator can only be accessed from exactly one compute node. While this static mapping enables efficient data transfers between a given accelerator and the compute node it belongs to, differing computational demands across jobs may, however, produce either underutilized accelerators or nodes whose computational demands cannot be satisfied with the number of accelerators available to them. In particular, smaller numbers of GPUs available per node may enforce explicit MPI parallelism across compute nodes where it is not necessary. To address this limitation, we propose a novel accelerator-cluster architecture in which network-attached accelerators are dynamically assigned to compute nodes. This allows not only their optimal utilization but also a more precise match between application requirements and accelerator hardware. We outline the general concept of our dynamic architecture and show that it can offer substantial benefits to certain classes of applications without significantly harming the performance of others. © 2012 IEEE.

关键词： Memory architecture

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Periodic hierarchical load balancing for large supercomputers

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INTERNATIONAL JOURNAL OF HIGH PERFORMANCE COMPUTING APPLICATIONS 2011年第4期25卷 371-385页

作者： Zheng, Gengbin Bhatele, Abhinav Meneses, Esteban Kale, Laxmikant V. Univ Illinois Dept Comp Sci Urbana IL 61801 USA Univ Illinois Parallel Programming Lab Urbana IL 61801 USA

Large parallel machines with hundreds of thousands of processors are becoming more prevalent. Ensuring good load balance is critical for scaling certain classes of parallel applications on even thousands of processors. Centralized load balancing algorithms suffer from scalability problems, especially on machines with a relatively small amount of memory. Fully distributed load balancing algorithms, on the other hand, tend to take longer to arrive at good solutions. In this paper, we present an automatic dynamic hierarchical load balancing method that overcomes the scalability challenges of centralized schemes and longer running times of traditional distributed schemes. Our solution overcomes these issues by creating multiple levels of load balancing domains which form a tree. This hierarchical method is demonstrated within a measurement-based load balancing framework in CHARM++. We discuss techniques to deal with scalability challenges of load balancing at very large scale. We present performance data of the hierarchical load balancing method on up to 16,384 cores of Ranger (at the Texas Advanced Computing Center) and 65,536 cores of Intrepid (the Blue Gene/P at Argonne National Laboratory) for a synthetic benchmark. We also demonstrate the successful deployment of the method in a scientific application, NAMD, with results on Intrepid.

关键词： hierarchical algorithms load balancing parallel applications performance study scalability

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Using shared arrays in message-driven parallel programs

Using shared arrays in message-driven parallel programs

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25th IEEE International parallel and Distributed Processing Symposium, Workshops and Phd Forum, IPDPSW 2011

作者： Miller, Phil Becker, Aaron Kalé, Laxmikant Parallel Programming Laboratory Department of Computer Science University of Illinois Urbana-Champaign United States

ISBN: (纸本)9780769543857

This paper describes a safe and efficient combination of the object-based message-driven execution and shared array parallel programming models. In particular, we demonstrate how this combination engenders the composition of loosely coupled parallel modules safely accessing a common shared array. That loose coupling enables both better flexibility in parallel execution and greater ease of implementing multi-physics simulations. As a case study, we describe how the parallelization of a new method for molecular dynamics simulation benefits from both of these advantages. We also describe a system of typed handle objects that embed some of the determinacy constraints of the Multiphase Shared Array programming model in the C type system, to catch some violations at compile time. The combined programming model communicates in terms of these handles as a natural means of detecting and preventing errors. © 2011 IEEE.

关键词： Molecular dynamics

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Using Shared Arrays in Message-Driven parallel Programs

Using Shared Arrays in Message-Driven Parallel Programs

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IEEE International Symposium on parallel and Distributed Processing Workshops and Phd Forum (IPDPSW)

作者： Phil Miller Aaron Becker Laxmikant Kale Parallel Programming Laboratory Department of Computer Science University of Illinois Urbana-Champaign USA

This paper describes a safe and efficient combination of the object-based message-driven execution and shared array parallel programming models. In particular, we demonstrate how this combination engenders the composition of loosely coupled parallel modules safely accessing a common shared array. That loose coupling enables both better flexibility in parallel execution and greater ease of implementing multi-physics simulations. As a case study, we describe how the parallelization of a new method for molecular dynamics simulation benefits from both of these advantages. We also describe a system of typed handle objects that embed some of the determinacy constraints of the Multiphase Shared Array programming model in the C++ type system, to catch some violations at compile time. The combined programming model communicates in terms of these handles as a natural means of detecting and preventing errors.

关键词： Arrays Message systems Synchronization Instruction sets Runtime Phased arrays programming

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Patterns of inefficient performance behavior in GPU applications

Patterns of inefficient performance behavior in GPU applicat...

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19th International Euromicro Conference on parallel, Distributed and Network-Based Processing (PDP)

作者： Eschweiler, Dominic Becker, Daniel Wolf, Felix Forschungszentrum Julich Julich Supercomp Ctr D-52428 Julich Germany German Res Sch Simulat Sci Lab Parallel Programming D-52062 Aachen Germany Rhein Westfal TH Aachen Dept Comp Sci D-52056 Aachen Germany

ISBN: (纸本)9780769543284

Writing efficient software for heterogeneous architectures equipped with modern accelerator devices presents a serious challenge to programmer productivity, creating a need for powerful performance-analysis tools to adequately support the software development process. To guide the design of such tools, we describe typical patterns of inefficient runtime behavior that may adversely affect the performance of applications that use general-purpose processors along with GPU devices through a CUDA compute engine. To evaluate the general impact of these patterns on application performance, we further present a microbenchmark suite that allows the performance penalty of each pattern to be quantified with results obtained on NVIDIA Fermi and Tesla architectures, indeed demonstrating significant delays. Furthermore this suite can be used as a default test scenario to add CUDA support to performance-analysis tools used in high-performance computing.

关键词： analysis cuda patterns performance tools EQUIPMENT performance behavior GRAPPER PICK UP Graphics Processing Unit High Performance Computing ARCHITECTURE

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