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Fretting wear mechanism of GH4169 dovetail joint specimens treated with hybrid laser shock peening

Tribology International 2025年 209卷

作者： Fang, Xiuyang Wang, Zheng Wahab, Magd Abdel Gong, Jianen Liu, Xiong Liu, Xing Cai, Zhenbing School of Mechanical Engineering Southwest Jiaotong University Chengdu610031 China Tribology Research Institute Key Lab of Advanced Technologies of Materials Southwest Jiaotong University Chengdu610031 China Soete Laboratory Department of Electrical Energy Metals Mechanical Constructions and Systems Faculty of Engineering and Architecture Ghent University Gent9000 Belgium College of Engineering Yuan Ze University Taiwan China Parallel and Distributed Systems Laboratory Jožef Stefan Institute Jamova cesta 39 LjubljanaSI-1000 Slovenia DongFang Electric Machinery Co. LTD Deyang618000 China State Key Laboratory of Advanced Electromagnetic Technology Huazhong University of Science and Technology Hubei Wuhan430074 China

Aero engine blade structure is prone to severe fretting wear under centrifugal forces and vibration loads, resulting in greatly reduced engine service life, which is a typical fretting damage problem. In this paper, without Absorbing layer Nanosecond Laser Shock Peening (wAN-LSP) and without Absorbing layer Nanosecond superimposed Femtosecond hybrid Laser Shock Peening (NF-LSP) are utilized to strengthen the surface of GH4169 dovetail joint specimens, which is a common material for engine blades, to explore its strengthening mechanism and fretting wear evolution law. The findings indicate that the surface roughness of the wAN-LSP specimen rises from 0.28 μm to 1.16 μm. The thermal effects of wAN-LSP lead to the formation of a molten layer roughly 10.97 μm thick on the surface, accompanied by numerous pits, ablation holes, and micro-cracks. In contrast, NF-LSP treatment effectively eliminates the surface oxidation defects made by the thermal effects of wAN-LSP, leading to a slight decrease in surface roughness. Both wAN-LSP and NF-LSP treatments enhance the surface hardness of the specimens, creating a plastic deformation layer roughly 400 μm deep, but the near surface hardness of NF-LSP treated specimen is further improved compared to that of the wAN-LSP specimen. The wear mechanism observed in the GH4169 dovetail joint specimens following wAN-LSP and NF-LSP treatment are identified as abrasive wear and oxidation wear. Initially, as the number of cycles raises, the wear volume of GH4169 specimen treated with wAN-LSP is higher than that of untreated specimen, but subsequently, it becomes lesser than that of the untreated specimen. This phenomenon results from the interplay between the molten layer and hardened layer. In the initial stage of wear, despite the surface strengthening of the wAN-LSP specimen, the presence of molten layer significantly diminishes the fretting wear resistance of the material. As wear progresses, the molten layer is removed, revealing the be

关键词： Abrasion

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TurboTag: Lookup filtering to reduce coherence directory power 10

TurboTag: Lookup filtering to reduce coherence directory pow...

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Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design

作者： Lotfi-Kamran, Pejman Ferdman, Michael Crisan, Daniel Falsafi, Babak Parallel Systems Architecture Lab École Publique Polytechnique Fédérale de Lausanne Switzerland Computer Architecture Lab Carnegie Mellon University United States

ISBN: (纸本)9781450301466

On-chip coherence directories of today's multi-core systems are not energy efficient. Coherence directories dissipate a significant fraction of their power on unnecessary lookups when running commercial server and scientific workloads. These workloads have large working sets that are beyond the reach of on-chip caches of modern processors. Limited to capturing a small part of the working set, private caches retain cache blocks only for a short period of time before replacing them with new blocks. Moreover, coherence enforcement is a known performance bottleneck of multi-threaded software, hence data-sharing in optimized high-performance software is minimal. Consequently, the majority of the accesses to the coherence directory find no sharers in the directory because the data are not available in the on-chip private caches, effectively wasting power on the coherence checks. To improve energy-efficiency for future many-core systems, we propose TurboTag, a filtering mechanism to eliminate needless directory lookups. We analyze full-system traces of server and scientific workloads and find that over 69% of accesses to the directory find no sharers and can be entirely avoided. Taking advantage of this behavior, TurboTag achieves a 58% reduction in the directory's dynamic power consumption. Copyright 2010 ACM.

关键词： Bandpass filters

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Energy efficiency of heterogeneous multicore system based on the enhanced Amdahl's law

Energy efficiency of heterogeneous multicore system based on...

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作者： Pei, Songwen Zhang, Junge Xiong, Naixue Kim, Myoung-Seo Gaudiot, Jean-Luc Shanghai Key Lab of Modern Optical Systems University of Shanghai for Science and Technology Shanghai200093 China Parallel Systems and Computer Architecture Lab University of California IrvineCA92697 United States

Energy efficiency is one of the biggest challenges of designing future heterogeneous multicore system, beyond performance, hereby, we propose an energy efficiency analytical model for heterogeneous multicore system based on the enhanced Amdahl's law. The model extends the traditional computing-centric model by considering the overhead of data preparation which potentially includes the overhead of communication, data transfer, synchronisation, etc. The analysis clearly shows that decreasing the overhead of data preparation is a promising approach to reach higher performance of computation and greater energy efficiency. Therefore, more informed trade-offs should be taken when we design a modern heterogeneous processor system within limited budget of energy. © 2018 Inderscience Enterprises Ltd.

关键词： Energy efficiency

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Codelet Scheduling by Genetic Algorithm

Codelet Scheduling by Genetic Algorithm

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IEEE International Conference on Trust, Security and Privacy in Computing and Communications (TrustCom)

作者： Songwen Pei Jinkai Wang Wenyang Cui Linhua Jiang Tongsheng Geng Jean-Luc Gaudiot Stéphane Zuckerman Shanghai Key Lab of Modern Optical Systems University of Shanghai for Science and Technology Shanghai China Parallel Systems and Computer Architecture Lab University of California Irvine CA USA Computer Architecture & Parallel Systems Laboratory University of Delaware Newark DE

ISBN: (纸本)9781509032068

Codelet model is a fine-grained, event-driven hybrid parallel model inspired by dataflow, whose performance depends on the scheduling policy. How to design optimal codelet scheduling policy based on the features of tasks is important to the codelet-based system performance. In this paper, we propose an adaptive codelet scheduling policy by combing "pure" genetic algorithm for tasks with complex dependencies. It is verified that the policy is effective based on bunches of experimental results.

关键词： Computational modeling Schedules Genetic algorithms Scheduling Runtime Optimal scheduling Sociology

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Cuckoo directory: A scalable directory for many-core systems

Cuckoo directory: A scalable directory for many-core systems

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IEEE Symposium on High-Performance Computer architecture

作者： Michael Ferdman Pejman Lotfi-Kamran Ken Balet Babak Falsafi Computer Architecture Lab Carnegie Mellon University USA Parallel Systems Architecture Lab école Polytechnique Fédérale de Lausanne Switzerland

Growing core counts have highlighted the need for scalable on-chip coherence mechanisms. The increase in the number of on-chip cores exposes the energy and area costs of scaling the directories. Duplicate-tag-based directories require highly associative structures that grow with core count, precluding scalability due to prohibitive power consumption. Sparse directories overcome the power barrier by reducing directory associativity, but require storage area over-provisioning to avoid high invalidation rates. We propose the Cuckoo directory, a power- and area-efficient scalable distributed directory. The cuckoo directory scales to high core counts without the energy costs of wide associative lookup and without gross capacity over-provisioning. Simulation of a 16-core CMP with commercial server and scientific workloads shows that the Cuckoo directory eliminates invalidations while being up to four times more power-efficient than the Duplicate-tag directory and 24% more power-efficient and up to seven times more area-efficient than the Sparse directory organization. Analytical projections indicate that the Cuckoo directory retains its energy and area benefits with increasing core count, efficiently scaling to at least 1024 cores.

关键词： Organizations Coherence Scalability Aggregates System-on-a-chip Servers Hardware

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Towards Autoscaling with Guarantees on Kubernetes Clusters

Towards Autoscaling with Guarantees on Kubernetes Clusters

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Autonomic Computing and Self-Organizing systems Companion (ACSOS-C), IEEE International Conference on

作者： Stephen Burroughs Helge Dickel Martin van Zijl Vladimir Podolskiy Michael Gerndt Robi Malik Panos Patros ORKA Cloud and Adaptive Systems Lab University of Waikato New Zealand Chair of Computer Architecture and Parallel Systems Technical University of Munich Germany

Autoscaling is used by cloud providers, microser-vices, and edge computing applications to respond to dynamic load fluctuations. A critical direction of research has focused on providing guarantees under uncertainty that the auto scaling system will work as intended-both at design-time and more importantly, at runtime. In this work, we evaluate the efficacy of three complementary methods: A) deterministic finite automata, B) probabilistic process algebra and C) Proportional-Integral-Derivative (PID) control. We experimentally evaluate their efficacy in modelling and verify autoscaling on clusters managed by Kubernetes. Our results suggest that deterministic modelling can provide theoretically optimal guarantees for small deployments; probabilistic algebras are able to capture stochastic behaviours, but benefit from deterministic templates; and control theory benefits by providing a black-box approach for modelling, verification and control.

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Dynamic register file partitioning in superscalar microprocessors for energy efficiency

Dynamic register file partitioning in superscalar microproce...

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Meltem Özsoy Y. Onur Koçberber Mehmet Kayaalp Oğuz Ergin State University of New York Binghamton USA State University of New York Binghamton EPFL - Parallel Systems Architecture Lab (PARSA) Turkey TOBB University of Economics and Technology Turkey

Register file is one of the vital and energy consuming parts inside microprocessor. Many studies show that it is one of the hot spots on the chip. It is also observed by many researchers that many of the produced values in a processor are narrow. By using the narrow values, register files can store fewer bits and may be designed to need less static and dynamic energy. In this paper we propose a register file design that stores data in narrow value groups and values are written to those groups according to their widths. Size of narrow value groups can be set dynamically according to the behavior of the program while having the same performance. We show that the register file which has dynamically changing narrow value groups offers static and dynamic energy savings in the register file up to 65% with negligible performance loss.

关键词： Transistors Sleep

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A systematic mapping study in AIOps

arXiv

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arXiv 2020年

作者： Notaro, Paolo Cardoso, Jorge Gerndt, Michael Chair of Computer Architecture and Parallel Systems Technical University of Munich Germany Ultra-scale AIOps Lab Huawei Munich Research Center Germany Department of Informatics Engineering/CISUC University of Coimbra Portugal

IT systems of today are becoming larger and more complex, rendering their human supervision more difficult. Artificial Intelligence for IT Operations (AIOps) has been proposed to tackle modern IT administration challenges thanks to AI and Big Data. However, past AIOps contributions are scattered, unorganized and missing a common terminology convention, which renders their discovery and comparison impractical. In this work, we conduct an in-depth mapping study to collect and organize the numerous scattered contributions to AIOps in a unique reference index. We create an AIOps taxonomy to build a foundation for future contributions and allow an efficient comparison of AIOps papers treating similar problems. We investigate temporal trends and classify AIOps contributions based on the choice of algorithms, data sources and the target components. Our results show a recent and growing interest towards AIOps, specifically to those contributions treating failure-related tasks (62%), such as anomaly detection and root cause analysis. © 2020, CC BY.

关键词： Artificial intelligence

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ReSim, a trace-driven, reconfigurable ILP processor simulator 09

ReSim, a trace-driven, reconfigurable ILP processor simulato...

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Design, Automation and Test in Europe Conference and Exhibition

作者： Sotiria Fytraki Dionisios Pnevmatikatos Department of Electronic and Computer Engineering Technical University of Crete Chania Greece Parallel Systems Architecture Lab (PARSA) Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland FORTH-ICS Greece

ISBN: (纸本)9783981080155

Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration relies on extensive use of software simulation that when highly accurate is slow. In this paper we propose ReSim, a parameterizable ILP processor simulation acceleration engine based on reconfigurable hardware. We describe ReSim's trace-driven microarchitecture that allows us to simulate the operation of a complex ILP processor in a cycle serial fashion, aiming to simplify implementation complexity and to boost operating frequency. Being trace driven, ReSim can simulate timing in an almost ISA independent fashion, and supports all SimpleScalar ISAs, i.e. PISA, Alpha, etc. We implemented ReSim for the latest Xilinx devices. In our experiments with a 4-way superscalar processor ReSim achieves a simulation throughput of up to 28MIPS, and offers more than a factor of 5x improvement over the best reported ILP processor hardware simulators.

关键词： Hardware Instruction sets Application software Space exploration Acceleration Engines Microarchitecture Frequency Timing Throughput

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Large-throughput parallel optical interconnection for a distributed parallel computing system

Large-throughput parallel optical interconnection for a dist...

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1999 Pacific Rim Conference on Lasers and Electro-Optics, CLEO/Pacific Rim 1999

作者： Nishimura, S. Harasawa, K. Matsudairn, N. Akutsu, S. Sasaki, S. Kudoh, T. RWCP Optical Interconnection Hitachi Laboratory C/o Central Research Lab Hitachi Ltd. 1-280 Higashi-koigakubo Kokubunji-shi Tokyo185-8601 Japan Hitachi Communication Systems Inc. 180 Totsuka-cho Totsuka-ku Yokohama244-0003 Japan RWCP Parallel and Distributed System Architecture Lab. Tsukuba Mitsui Building I6F 1-6-1 Takezono Tsukuba-shi Ibaraki305-0032 Japan

We produced a large-throughput optical interconnection for a distributed parallel computing system. It transmits optical data at a rate of over 800-Mbit/s×10-bit through a 50-m single-mode fiber, using a CMOS MUX... 详细信息

ISBN: (纸本)0780356616

关键词： Single mode fibers

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