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10th International Symposium on Quality Electronic Design

作者： Liu, Feng Mohamed, Otmane Ait Song, Xiaoyu Tan, Qingping National Lab of Parallel Distributed Processing Hunan China ECE department Concordia University Montreal QC Canada ECE department Portland State University Portland OR United States

ISBN: (纸本)9781424429523

The paper presents a novel and synergistic system-level modeling approach based on aspect-oriented programming (AOP) and SystemC. A case study on a 128-bit binary floating-point adder is performed to demonstrate the modeling strength of the approach. The validation experiment shows the effectiveness of the proposed approach. This work constitutes a first attempt to employ AOP in modeling digital systems.

关键词： System-Level Modeling AOP SystemC

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A high efficient in-place transposition scheme for multidimensional arrays

A high efficient in-place transposition scheme for multidime...

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3rd International Conference on Information and Computing, ICIC 2010

作者： Yuan, Jie Wu, Jian-Ping Wang, Zheng-Hua National Lab. of Parallel and Distributed Processing National University of Defense Technology Changsha China School of Computer Science National University of Defense Changsha China

ISBN: (纸本)9780769540474

This paper presents a in-place cycle-reducing method for multidimensional arrays transposition in local memory to reduce the memory R/W operations. The resulting method can significantly reduce the number of subcycles (also called following-cycles) and that of memory operations for square arrays. Taking square array 256 by 256 for example, the number of subcycles used by current available best algorithm can be reduced from 32894 to only 574, using our new method, and the memory operation number can be reduced by about 32.58%, from 98430 to 66366. Taking advantage of this new method, the elapsed time can be reduced as a result. The number of cycles and operations can also be reduced for 2D rectangle arrays with 2m rows and 2n column stored in column-major, especially n=2m, even though the improvement is not as significant as that for square arrays. The improved 2D in-place algorithm has been extended to 3D arrays, and some theoretic and numerical results are also provided. Furthermore, we develop a new in-place 3D arrays transposition algorithm. This algorithm is very important for a deep research for multidimensional arrays. Experimental results show that our algorithm can improve efficiency significantly, compared to some other 3D array transposition schemes. © 2010 IEEE.

关键词： Multidimensional array Memory operation Cycle-reducing Transposition In-place transposition Transposition arrays three-dimensional array Local Memory MULTIDIMENSIONAL

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parallel transposing and communication strategies for FFT on cluster of SMP architectures with multicore processors

Parallel transposing and communication strategies for FFT on...

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Congress on Image and Signal processing, CISP

ISBN: (纸本)9781424465149

This paper presents a high performance parallel formulation for 1-D FFT based on transpose algorithm. The parallel scheme of FFT trades off some efficiency for a more consistent level of parallel performance. It involves matrix transposition, and a new in-place transposing algorithm is introduced into the parallel matrix transposition to improve the efficiency. Depending on the size of the input n, the number of processes p, and the memory or network bandwidth, this method can achieve better parallel performance than the other on cluster of SMP architectures. Test shows us that our scheme can achieve a good speedup. ©2010 IEEE.

关键词： Fast Fourier transforms

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An optimized method for automatic test oracle generation from real-time specification

An optimized method for automatic test oracle generation fro...

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IEEE International Conference on Engineering of Complex Computer Systems

作者： Xin Wang Zhi-Chang Qi Shuhao Li National Laboratory for Parallel and Distributed Processing Changsha China National Lab. for Parallel & Distributed Process. Changsha China

Test oracles are widely used to verify whether a system under test is running as desired. Since the correctness of real-time systems depends on the logical results of the computation and the time when results are produced at the same time, an optimized model checking-based method for test oracles generation is proposed to check if the system traces satisfy their real-time specifications at run time. Inspired by the idea of real-time model checking, the test oracles can be automatically generated from their specifications in the real-time logic MITL/sub [o,d]/ in a simpler way and modelled by a variant of the timed automata. Assertions are chosen to acquire the traces of real-time systems. A case study is presented to demonstrate the usefulness of the method proposed in this paper.

关键词： Optimization methods Automatic testing Real time systems System testing Software testing laboratories Logic testing Automata Aerospace testing distributed processing

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A Comparative Study of parallel Prefix Adders in FPGA Implementation of EAC

A Comparative Study of Parallel Prefix Adders in FPGA Implem...

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12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

作者： Liu, Feng Fariborz, F. F. Mohamed, Otmane Ait Chen, Gang Song, Xiaoyu Tan, Qingping National Lab. of Parallel Distributed Processing Hunan China ECE Department Concordia University Montreal QC Canada Lingcore Lab. Portland OR United States ECE Department Portland State University Portland OR United States

ISBN: (纸本)9780769537825

Several regular parallel trees have been proposed over the years to optimize logic depth, area, fan-out and interconnect count for logic circuits. In this paper, we propose a comparative study of different parallel prefix trees used in the design of a new end-around carry (EAC) adder targeting FPGA technology. This new adder is based on the fast 128-bit binary floating-point EAC adder which has been implemented in the IBM POWER6 microprocessor's fused multiply-add unit. The parallel prefix tree implemented on the IBM's EAC adder is a Kogge-Stone tree which has been chosen for its high performance and its low power consumption. Our comparative study highlights the main performance differences among fourteen different architecture configurations when targeting an FPGA EAC adder design. We focus on the area requirements and the critical path delay of these designs. Our experimental results show that there is one architecture configuration with the lower area requirement and the higher performance.

关键词： Adders

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Coverage problem in wireless sensor network: A survey

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Journal of Networks 2010年第9期5卷 1033-1040页

作者： Fan, Gao Jun Jin, Shi Yao National Lab of Parallel and Distributed Processing National University of Defense Technology Chang Sha China

Wireless sensor networks constitute the platform of a broad range of applications related to national security, surveillance, military, health care, and environmental monitoring. The coverage of WSN has answered the questions about quality of service (surveillance) which can be provided by WSN. Therefore, maximizing coverage using the resource constrained nodes is a non-trivial problem. The coverage problem for wireless sensor network (WSN) has been studied extensively in recent years, especially when combined with connectivity and energy efficiency. In this paper we present a survey of coverage problem. And besides some basic design considerations in coverage of WSN we describe two challenges, namely, maximizing network lifetime and network connectivity. We also provide a brief summary and comparison of existing coverage schemes. © 2010 ACADEMY PUBLISHER.

关键词： Wireless sensor networks

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Reducing cache contention in a multi-core processor via a scheduler

Reducing cache contention in a multi-core processor via a sc...

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International Conference on Advanced Computer Theory and Engineering

作者： Shekofteh, S. Kazem Deldari, Hossein Khalkhali, Maryam Baradaran Parallel and Distributed Processing Lab. Department of Computer Engineering Ferdowsi University of Mashhad Mashhad Iran Department of Computer Engineering Islamic Azad University Mashhad Branch Mashhad Iran

ISBN: (纸本)9781424465408

Multi-core architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance. Well scheduling of running threads on these processors will result in achieving higher performance. Modern multi-core systems are designed to allow clusters of cores to share various hardware structures, such as last-level caches, memory controllers, and interconnections, as well as prefetching hardware. Without considering these shared resources, scheduling the threads will cause serious degradation in overall performance of the system. In this paper we propose a novel algorithm to schedule the threads that considers these potential contentions to keep away from. The simulation results showed that the proposed scheduler would avoid from lots of contentions between threads on various resources especially on shared caches. © 2010 IEEE.

关键词： Scheduling

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AOP-based high-level power estimation in SystemC 10

AOP-based high-level power estimation in SystemC

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20th Great Lakes Symposium on VLSI, GLSVLSI 2010

作者： Liu, Feng Tan, Qingping Song, Xiaoyu Abbasi, Naeem National Lab. of Parallel Distributed Processing China ECE Dept. Portland State University Portland OR United States ECE Dept. Concordia University Montreal QC Canada

The paper presents a novel high-level power modeling and estimation framework. The approach is based on a synergic integration of aspect-oriented programming(AOP) and SystemC. Macro module modeling and power estimatio... 详细信息

ISBN: (纸本)9781450300124

关键词： Aspect oriented programming

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Hermes: An Optimization of HyperLogLog Counting in Real-time Data processing

Hermes: An Optimization of HyperLogLog Counting in Real-time...

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International Joint Conference on Neural Networks

作者： Yunxiang Zhao Songtao Guo Yuanyuan Yang National Lab for Parallel and Distributed Processing Southwest University Stony Brook University

ISBN: (纸本)9781509006212

HyperLogLog Counting is widely used in cardinality estimation. It is the foundation of many algorithms in data analysis, commodity recommendation and database optimization. Facing the large scale internet business like electronic commerce, internet companies have an urgent requirement of distributed real-time cardinality estimation with high accuracy and low time cost. In this paper, we propose a distributed real-time cardinality estimation algorithm named Hermes. Hermes adjusts the estimated cardinality dynamically according to the result of HyperLogLog Counting and also optimizes the data distribution strategy of existing distributed cardinality estimation algorithms. Experiments have been carried out and the results show that Hermes has lower estimation error and time cost compared with existing algorithms.

关键词： Estimation Real-time systems Algorithm design and analysis distributed databases Optimization Sparks Companies

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Raw Ultrasound-Based Phonetic Segments Classification Via Mask Modeling 48

Raw Ultrasound-Based Phonetic Segments Classification Via Ma...

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48th IEEE International Conference on Acoustics, Speech and Signal processing, ICASSP 2023

作者： You, Kang Liu, Bo Xu, Kele Xiong, Yunsheng Xu, Qisheng Feng, Ming Csapó, Tamás Gábor Zhu, Boqing Tongji University Shanghai China National University of Defense Technology Changsha China National Key Lab of Parallel and Distributed Processing Changsha China Budapest University of Technology and Economics Budapest Hungary

ISBN: (纸本)9781728163277

Ultrasound tongue imaging is widely used in clinical linguistics and phonetics. Recently, deep neural networks, especially convolutional neural networks, have been widely used in the interpretation and analysis of ultrasound tongue images (UTI). Despite achieving satisfactory performance, deep models rely on a large amount of manually labeled data, which is often difficult to obtain in practical settings. To address this issue, this paper focuses on how to utilize a large amount of unlabeled UTI data to improve the performance of UTI classification task. Specifically, we explore self-supervised learning with masking modeling strategy. By predicting the masked part, our pre-trained model enables the neural network to infer contextual information. Then, we fine-tune the pre-trained model with a small amount of labeled data. Compared with the previous competing algorithms, our method can improve the classification accuracy by an average of 13.33% in four different scenarios. © 2023 IEEE.

关键词： Mask modeling Masked auto-encoder Self-supervised learning Ultrasound tongue imaging.

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