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Model transformation based verification of Web services composition

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4th International Conference on Grid and Cooperative Computing - GCC 2005

作者： Yang, YanPing Tan, QingPing Xiao, Yong School of Computer Science National University of Defense Technology Changsha 410073 China National Lab. of Parallel Distributed Processing Changsha 410073 China

ISBN: (纸本)3540305106

Current Web services composition proposals, such as BPEL, BPSS, BPMN and WSCI, provide notations for describing the control and message flows in Web service collab.rations. However, such proposals remain at the descriptive level, without providing any kind of mechanisms or tool support for verifying the composition specified in the proposed notations. In this paper, we present to analyze and verify Web services composition by using CP-nets. CP-nets combine the strengths of Petri nets with the expressive power of high-level programming and have sound mathematical semantics. These services composition proposals can be transformed by model transformation rules into CP-nets, which can be used to analyze the performance and to investigate behavioral properties by CP-nets specialized tools. © Springer-Verlag Berlin Heidelberg 2005.

关键词： World Wide Web

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A Comparative Study of parallel Prefix Adders in FPGA Implementation of EAC

A Comparative Study of Parallel Prefix Adders in FPGA Implem...

引用

12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

作者： Liu, Feng Fariborz, F. F. Mohamed, Otmane Ait Chen, Gang Song, Xiaoyu Tan, Qingping National Lab. of Parallel Distributed Processing Hunan China ECE Department Concordia University Montreal QC Canada Lingcore Lab. Portland OR United States ECE Department Portland State University Portland OR United States

ISBN: (纸本)9780769537825

Several regular parallel trees have been proposed over the years to optimize logic depth, area, fan-out and interconnect count for logic circuits. In this paper, we propose a comparative study of different parallel prefix trees used in the design of a new end-around carry (EAC) adder targeting FPGA technology. This new adder is based on the fast 128-bit binary floating-point EAC adder which has been implemented in the IBM POWER6 microprocessor's fused multiply-add unit. The parallel prefix tree implemented on the IBM's EAC adder is a Kogge-Stone tree which has been chosen for its high performance and its low power consumption. Our comparative study highlights the main performance differences among fourteen different architecture configurations when targeting an FPGA EAC adder design. We focus on the area requirements and the critical path delay of these designs. Our experimental results show that there is one architecture configuration with the lower area requirement and the higher performance.

关键词： Adders

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A high efficient in-place transposition scheme for multidimensional arrays

A high efficient in-place transposition scheme for multidime...

引用

3rd International Conference on Information and Computing, ICIC 2010

作者： Yuan, Jie Wu, Jian-Ping Wang, Zheng-Hua National Lab. of Parallel and Distributed Processing National University of Defense Technology Changsha China School of Computer Science National University of Defense Changsha China

ISBN: (纸本)9780769540474

This paper presents a in-place cycle-reducing method for multidimensional arrays transposition in local memory to reduce the memory R/W operations. The resulting method can significantly reduce the number of subcycles (also called following-cycles) and that of memory operations for square arrays. Taking square array 256 by 256 for example, the number of subcycles used by current availab.e best algorithm can be reduced from 32894 to only 574, using our new method, and the memory operation number can be reduced by about 32.58%, from 98430 to 66366. Taking advantage of this new method, the elapsed time can be reduced as a result. The number of cycles and operations can also be reduced for 2D rectangle arrays with 2m rows and 2n column stored in column-major, especially n=2m, even though the improvement is not as significant as that for square arrays. The improved 2D in-place algorithm has been extended to 3D arrays, and some theoretic and numerical results are also provided. Furthermore, we develop a new in-place 3D arrays transposition algorithm. This algorithm is very important for a deep research for multidimensional arrays. Experimental results show that our algorithm can improve efficiency significantly, compared to some other 3D array transposition schemes. © 2010 IEEE.

关键词： Multidimensional array Memory operation Cycle-reducing Transposition In-place transposition Transposition arrays three-dimensional array Local Memory MULTIDIMENSIONAL

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parallel transposing and communication strategies for FFT on cluster of SMP architectures with multicore processors

Parallel transposing and communication strategies for FFT on...

引用

Congress on Image and Signal processing, CISP

ISBN: (纸本)9781424465149

This paper presents a high performance parallel formulation for 1-D FFT based on transpose algorithm. The parallel scheme of FFT trades off some efficiency for a more consistent level of parallel performance. It involves matrix transposition, and a new in-place transposing algorithm is introduced into the parallel matrix transposition to improve the efficiency. Depending on the size of the input n, the number of processes p, and the memory or network bandwidth, this method can achieve better parallel performance than the other on cluster of SMP architectures. Test shows us that our scheme can achieve a good speedup. ©2010 IEEE.

关键词： Fast Fourier transforms

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Reducing cache contention in a multi-core processor via a scheduler

Reducing cache contention in a multi-core processor via a sc...

引用

International Conference on Advanced Computer Theory and Engineering

作者： Shekofteh, S. Kazem Deldari, Hossein Khalkhali, Maryam Baradaran Parallel and Distributed Processing Lab. Department of Computer Engineering Ferdowsi University of Mashhad Mashhad Iran Department of Computer Engineering Islamic Azad University Mashhad Branch Mashhad Iran

ISBN: (纸本)9781424465408

Multi-core architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance. Well scheduling of running threads on these processors will result in achieving higher performance. Modern multi-core systems are designed to allow clusters of cores to share various hardware structures, such as last-level caches, memory controllers, and interconnections, as well as prefetching hardware. Without considering these shared resources, scheduling the threads will cause serious degradation in overall performance of the system. In this paper we propose a novel algorithm to schedule the threads that considers these potential contentions to keep away from. The simulation results showed that the proposed scheduler would avoid from lots of contentions between threads on various resources especially on shared caches. © 2010 IEEE.

关键词： Scheduling

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AOP-based high-level power estimation in SystemC 10

AOP-based high-level power estimation in SystemC

引用

20th Great Lakes Symposium on VLSI, GLSVLSI 2010

作者： Liu, Feng Tan, Qingping Song, Xiaoyu Abbasi, Naeem National Lab. of Parallel Distributed Processing China ECE Dept. Portland State University Portland OR United States ECE Dept. Concordia University Montreal QC Canada

The paper presents a novel high-level power modeling and estimation framework. The approach is based on a synergic integration of aspect-oriented programming(AOP) and SystemC. Macro module modeling and power estimatio... 详细信息

ISBN: (纸本)9781450300124

关键词： Aspect oriented programming

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An optimized method for automatic test oracle generation from real-time specification

An optimized method for automatic test oracle generation fro...

引用

IEEE International Conference on Engineering of Complex Computer Systems

作者： Xin Wang Zhi-Chang Qi Shuhao Li National Laboratory for Parallel and Distributed Processing Changsha China National Lab. for Parallel & Distributed Process. Changsha China

Test oracles are widely used to verify whether a system under test is running as desired. Since the correctness of real-time systems depends on the logical results of the computation and the time when results are produced at the same time, an optimized model checking-based method for test oracles generation is proposed to check if the system traces satisfy their real-time specifications at run time. Inspired by the idea of real-time model checking, the test oracles can be automatically generated from their specifications in the real-time logic MITL/sub [o,d]/ in a simpler way and modelled by a variant of the timed automata. Assertions are chosen to acquire the traces of real-time systems. A case study is presented to demonstrate the usefulness of the method proposed in this paper.

关键词： Optimization methods Automatic testing Real time systems System testing Software testing lab.ratories Logic testing Automata Aerospace testing distributed processing

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Property-oriented test generation from UML Statecharts 04

Property-oriented test generation from UML Statecharts

引用

IEEE International Conference on Automated Software Engineering (ASE)

作者： Shuhao Li Ji Wang Zhi-ChangQi National Laboratory for Parallel and Distributed Processing Changsha P.R. China National Lab. for Parallel & Distributed Process. Changsha China

ISBN: (纸本)0769521312

UML Statecharts is an important modeling formalism with hierarchy, concurrency, broadcast-communication mechanisms and data variables. These facilities help the developers to describe the complex behaviors of an object along its lifecycle naturally. However, the ease of modeling is at the expense of testing: the system developed from Statecharts usually has numerous behaviors and is therefore extremely difficult to receive comprehensive and in-depth testing. This work presents an approach to deriving targeted test sequences from UML Statecharts according to tester-specified temporal logic properties. Using this approach, testing efforts can be focused on specific properties of the system and usually only a small portion of the total behaviors will be tested. This method suits well the occasions when the testers are interested in just some specific properties of the system or when they have to focus on its critical properties in case that limited budget is availab.e.

关键词： Unified modeling language Automatic testing Software testing Software engineering

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An efficient local address generation for the block-cyclic distribution 3

An efficient local address generation for the block-cyclic d...

引用

3rd International Conference on Algorithms and Architectures for parallel processing, ICA3PP 1997

作者： Kwon, Oh-Young Kim, Tae-Geun Han, Tack-Don Yang, Sung-Bong Kim, Shin-Dug Distributed Computing Lab. Systems Engineering Research Institute 1 Ueun-dong Yusong-gu Taejon305-333 Korea Republic of Parallel Processing System Laboratory Dept. of Computer Science Yonsei University Seoul120-749 Korea Republic of

ISBN: (纸本)0780342291

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time ΔM table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a ΔM table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time ΔM table generation method is faster than other algorithms in ΔM table generation time and access time for 10,000 array elements. © 1997 IEEE.

关键词： Virtual addresses

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Modelling with relational calculus of object and component systems - RCOS

Modelling with relational calculus of object and component s...

引用

作者： Chen, Zhenbang Hannousse, Abdel Hakim Van Hung, Dang Knoll, Istvan Li, Xiaoshan Liu, Zhiming Liu, Yang Nan, Qu Okika, Joseph C. Ravn, Anders P. Stolz, Volker Yang, Lu Zhan, Naijun International Institute for Software Technology United Nations University China Faculty of Science and Technology University of Macau Department of Computer Science Aalborg University Denmark Lab. of Computer Science Institute of Software CAS China National Laboratory for Parallel and Distributed Processing China

ISBN: (纸本)3540852883

This chapter presents a formalization of functional and behavioural requirements, and a refinement of requirements to a design for CoCoME using the Relational Calculus of Object and Component Systems (rCOS). We give a model of requirements based on an abstraction of the use cases described in Chapter 3.2. Then the refinement calculus of rCOS is used to derive design models corresponding to the top level designs of Chapter 3.4. We demonstrate how rCOS supports modelling different views and their relationships of the system and the separation of concerns in the development. © 2008 Springer-Verlag Berlin Heidelberg.

关键词： Calculations

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