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7th Asia-Pacific Web Conference on Web Technologies Research and Development - APWeb 2005

作者： Zhang, Xiaoyan Wang, Ting Tang, Jintao Zhou, Huiping Chen, Huowang National Laboratory for Parallel and Distributed Processing Changsha Hunan 410073 China

With the rapid growth of the available information on the Internet, it is more difficult for us to find the relevant information quickly on the Web. Named Entity Recognition (NER), one of the key techniques in some web information processing tools such as information retrieval and information extraction, has been paid more and more attention. In this paper we address the problem of Chinese NER using a hybrid-statistical model. This study is concentrated on entity names (personal names, location names and organization names), temporal expressions (dates and times) and number expressions. The method is characterized as follows: firstly, NER and Part-of-Speech tagging have been integrated into a unified framework;secondly, it combines Hidden Markov Model (HMM) with Maximum Entropy Model (MEM) by taking MEM as a sub-model invoked in Viterbi algorithm;thirdly, the Part-of-Speech information of the context has been used in MEM. The experiment shows that the hybrid-statistical model could achieve preferable results of Chinese NER, in which the F1 value ranges from 74% to 92% for all kinds of named entities on an open-test data. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Pattern recognition

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MilkyWay-2 supercomputer： system and application

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Frontiers of Computer Science 2014年第3期8卷 345-356页

作者： Xiangke LIAO Liquan XIAO Canqun YANG Yutong LU Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha 410073 China College of Computer National University of Defense Technology Changsha 410073 China

On June 17, 2013, MilkyWay-2 （Tianhe-2） supercomputer was crowned as the fastest supercomputer in the world on the 41th TOP500 list. This paper provides an overview of the MilkyWay-2 project and describes the design of hardware and software systems. The key architecture features of MilkyWay-2 are highlighted, including neo-heterogeneous compute nodes integrating commodity- off-the-shelf processors and accelerators that share similar instruction set architecture, powerful networks that employ proprietary interconnection chips to support the massively parallel message-passing communications, proprietary 16- core processor designed for scientific computing, efficient software stacks that provide high performance file system, emerging programming model for heterogeneous systems, and intelligent system administration. We perform extensive evaluation with wide-ranging applications from LINPACK and Graph500 benchmarks to massively parallel software deployed in the system.

关键词： MilkyWay-2 supercomputer petaflops computing neo-heterogeneous architecture interconnect network heterogeneous programing model system management benchmark optimization performance evaluation

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Mirror image:newfangled cell-level layout technique for single-event transient mitigation

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Chinese Science Bulletin 2014年第23期59卷 2850-2858页

作者： Pengcheng Huang Shuming Chen Zhengfa Liang Jianjun Chen Chunmei Hu Yibai He Micro-electronics and Microprocessor Institute National University of Defense Technology National Laboratory for Parallel and Distributed Processing National University of Defense Technology

Recent years,the hardening of combinational circuits is becoming a common *** the transistor-level hardening technique,the cell-level hardening technique,a divide and conquer strategy,can substantially make use of some typical character in the cell-circuit module to mitigate single event transient(SET)*** mirror image(MI)technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure.3D TCAD mixed-mode simulation have been performed in 65 nm twinwell bulk CMOS process,the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25%,and can mitigate the SET pulse width from the posterior-stage PMOS about 10%.The MI technique,a represent of the cell-level technique,may be the future of the hardening of combinational circuits.

关键词：单事件技术细胞瞬态镜像组合逻辑电路次布 CMOS工艺

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FPQRNA: Hardware-accelerated qrna package for noncoding rna gene detecting on FPGA

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Journal of Bioinformatics and Computational Biology 2010年第4期8卷 743-761页

作者： Xia, Fei Dou, Yong Lei, Guo-Qing National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 China

Noncoding RNAs (ncRNAs) have important functional roles in biological processes and have become a central research interest in modern molecular biology. However, how to find ncRNA attracts much more attention since ncRNA gene sequences do not have strong statistical signals, unlike protein coding genes. QRNA is a powerful program and has been widely used as an efficient analysis tool to detect ncRNA gene at present. Unfortunately, the O(L ³) computing requirements and complicated data dependency greatly limit the usefulness of QRNA package with the explosion in gene database. In this paper, we present a fine-grained parallel QRNA prototype system, FPQRNA, for accelerating ncRNA gene detection application on FPGA chip. We propose a systolic-like array architecture with multiple PEs (processing Elements). We partition the tasks by columns and assign tasks to PEs for load balance. We exploit data reuse schemes to reduce the need to load matrices from external memory. The experimental results show a speedup factor of more than 18× over the QRNA - 2.0.3c software running on a PC platform with AMD Phenom 9650 Quad CPU for pairwise sequence alignment with 996 residues, however the power consumption of our FPGA accelerator is only about 30% of that of the general-purpose microprocessors. © 2010 Imperial College Press.

关键词： Bioinformatics fine-grained parallelism FPGA hardware accelerator noncoding RNA

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The TH Express high performance interconnect networks

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Frontiers of Computer Science 2014年第3期8卷 357-366页

作者： Zhengbin PANG Min XIE Jun ZHANG Yi ZHENG Guibin WANG Dezun DONG Guang SUO Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha 410073 China College of Computer National University of Defense Technology Changsha 410073 China

Interconnection network plays an important role in scalable high performance computer （HPC） systems. The TH Express-2 interconnect has been used in MilkyWay-2 system to provide high-bandwidth and low-latency interprocessot communications, and continuous efforts are devoted to the development of our proprietary interconnect. This paper describes the state-of-the-art of our proprietary interconnect, especially emphasizing on the design of network interface. Several key features are introduced, such as user-level communication, remote direct memory access, offload collective operation, and hardware reliable end-to-end communication, etc. The design of a low level message passing infrastructures and an upper message passing services are also proposed. The preliminary performance results demonstrate the efficiency of the TH interconnect interface.

关键词： HPC network interface chip (NIC) TH Express nterconnect offload collective operation

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Towards estimating expected sizes of probabilistic skylines

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Science China(Information Sciences) 2011年第12期54卷 2574-2584页

作者： YANG YongTao & WANG YiJie National Key laboratory for parallel and distributed processing, School of Computer, National University of Defense Technology, Changsha 410073, China 1. National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

We consider the maximal vector problem on uncertain data, which has been recently posed by the study on processing skyline queries over a probabilistic data stream in the database context. Let D n be a set of n points in a d-dimensional space and q (0 < q 1) be a probability threshold; each point in D n has a probability to occur. Our problem is concerned with how to estimate the expected size of the probabilistic skyline, which consists of all the points that are not dominated by any other point in D n with a probability not less than q. We prove that the upper bound of the expected size is O(min{n, (- ln q)(ln n) d-1 }) under the assumptions that the value distribution on each dimension is independent and the values of the points along each dimension are distinct. The main idea of our proof is to find a recurrence about the expected size and solve it. Our results reveal the relationship between the probability threshold q and the expected size of the probabilistic skyline, and show that the upper bound is poly-logarithmic when q is not extremely small.

关键词： probabilistic skyline probabilistic data streams expected size

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Internet-based virtual computing environment(iVCE):Concepts and architecture

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Science in China(Series F) 2006年第6期49卷 681-701页

作者： LU Xicheng WANG Huaimin WANG Ji National Laboratory for Parallel and Distributed Processing Changsha 410073 China College of Computer National University of Defense Technology Changsha 410073 China

Resources over Internet have such intrinsic characteristics as growth, autonomy and diversity, which have brought many challenges to the efficient sharing and comprehensive utilization of these resources. This paper presents a novel approach for the construction of the Internet-based Virtual Computing Environment （iVCE）, whose sig- nificant mechanisms are on-demand aggregation and autonomic collaboration. The iVCE is built on the open infrastructure of the Internet and provides harmonious, transparent and integrated services for end-users and applications. The concept of iVCE is presented and its architectural framework is described by introducing three core concepts, i.e., autonomic element, virtual commonwealth and virtual executor. Then the connotations, functions and related key technologies of each components of the architecture are deeply analyzed with a case study, iVCE for Memory.

关键词： resource aggregation collaboration virtual computing environment Internet

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CWLP:coordinated warp scheduling and locality-protected cache allocation on GPUs

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Frontiers of Information Technology & Electronic Engineering 2018年第2期19卷 206-220页

作者： Yang ZHANG Zuo-cheng XING Cang LIU Chuan TANG National Laboratory for Parallel and Distributed Processing National University of Defense Technology

As we approach the exascale era in supercomputing, designing a balanced computer system with a powerful computing ability and low power requirements has becoming increasingly important. The graphics processing unit（GPU） is an accelerator used widely in most of recent supercomputers. It adopts a large number of threads to hide a long latency with a high energy efficiency. In contrast to their powerful computing ability, GPUs have only a few megabytes of fast on-chip memory storage per streaming multiprocessor（SM）. The GPU cache is inefficient due to a mismatch between the throughput-oriented execution model and cache hierarchy design. At the same time, current GPUs fail to handle burst-mode long-access latency due to GPU＇s poor warp scheduling ***, benefits of GPU＇s high computing ability are reduced dramatically by the poor cache management and warp scheduling methods, which limit the system performance and energy efficiency. In this paper, we put forward a coordinated warp scheduling and locality-protected（CWLP） cache allocation scheme to make full use of data locality and hide latency. We first present a locality-protected cache allocation method based on the instruction program counter（LPC） to promote cache performance. Specifically, we use a PC-based locality detector to collect the reuse information of each cache line and employ a prioritised cache allocation unit（PCAU） which coordinates the data reuse information with the time-stamp information to evict the lines with the least reuse possibility. Moreover, the locality information is used by the warp scheduler to create an intelligent warp reordering scheme to capture locality and hide latency. Simulation results show that CWLP provides a speedup up to 19.8% and an average improvement of 8.8% over the baseline methods.

关键词： Locality Graphics processing unit (GPU) Cache allocation Warp scheduling

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Simulation study of N-hit SET variation in differential cascade voltage switch logical circuits

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Science China(Information Sciences) 2015年第2期58卷 165-173页

作者： HUANG PengCheng CHEN ShuMing CHEN JianJun WU ZhenYu LIANG ZhengFa HU ChunMei LIANG Bin LIU BiWei Micro-electronics and Microprocessor Institute College of Computer ScienceNational University of Defense Technology National Laboratory for Parallel and Distributed Processing College of Computer ScienceNational University of Defense Technology

The advancement in the process leads to more concern about the Single Event(SE) sensitivity of the Differential Cascade Voltage Switch Logic(DCVSL) circuits. The simulation results indicate that the Single Event Transient(SET) generated at the DCVSL gate is much larger than that at the ordinary CMOS gate, and their SET variation is different. Based on charge collection, in this paper, the effective collection time theory is proposed to set forth the SET pulse generated at the DCVSL gate. Through 3D TCAD mixed-mode simulation in 65 nm twin-well bulk CMOS process, the effects on SET variation of device parameters such as well contact size and environment parameters such as voltage are investigated.

关键词： differential cascade voltage switch logic(DCVSL) single event transient(SET) effective collection time pulse feedback feature(PFF) across-coupled structure

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Providing Virtual Cloud for Special Purposes on Demand in JointCloud Computing Environment

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Journal of Computer Science & Technology 2017年第2期32卷 211-218页

作者： Dong-Gang Cao Member, CCF, IEEE, Bo An Pei-Chang Shi Huai-Min Wang Key Laboratory of High Confidence Software Technologies (Peking University) Ministry of Education Beijing 100871 China National Key Laboratory for Parallel and Distributed Processing National University of Defense and Technology Changsha 410073 China

Cloud computing has been widely adopted by enterprises because of its on-demand and elastic resource usage paradigm. Currently most cloud applications are running on one single cloud. However, more and more applications demand to run across several clouds to satisfy the requirements like best cost efficiency, avoidance of vender lock-in, and geolocation sensitive service. JointCloud computing is a new research initiated by Chinese institutes to address the computing issues concerned with multiple clouds. In JointCloud, users＇ diverse and dynamic requirements on cloud resources axe satisfied by providing users virtual cloud （VC） for special purposes. A virtual cloud for special purposes is in essence a user＇s specific cloud working environment having the customized software stacks, configurations and computing resources readily available. This paper first introduces what is JointCloud computing and then describes the design rationales, motivation examples, mechanisms and enabling technologies of VC in JointCloud.

关键词： cloud computing JointCloud virtual cloud (VC) cloud working environment

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