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IEEE International Conference on Communications (ICC)

作者： Shaohe Lv Weihua Zhuang Xiaodong Wang Chi Liu Xiaofeng Hu Yipin Sun Xingming Zhou Institute of Network Information and Security National University of Defense Technology Changsha China Department of Electrical and Computer Engineering University of Waterloo Waterloo ONT Canada Central South University Changsha China National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China

Successive interference cancellation (SIC) is an effective way of multipacket reception to combat interference. As conventional CSMA (Carrier Sense Multiple Access) is designed for single packet reception, it is unclear whether or not CSMA performs well to exploit the SIC capability. In this paper, we analyze the performance of a simple CSMA protocol in a network with SIC. For a given link, we derive the residing areas of an interfering node when simultaneous transmission is allowed and when the interference is harmful, respectively. We show that, though SIC provides many new transmission opportunities, CSMA cannot effectively exploit them. There is a fundamental tradeoff in a CSMA protocol between exploiting the transmission opportunities from SIC and capturing the harmful interference. In many cases, when CSMA achieves its best performance, almost all new transmission opportunities are not exploited. It is therefore very necessary to design a new distributed access protocol in wireless networks with SIC.

关键词： Silicon carbide Multiaccess communication Interference Receivers Propagation losses Protocols Wireless networks

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A Compact Model for Multi-Island Single Electron Transistors

A Compact Model for Multi-Island Single Electron Transistors

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3rd IEEE International NanoElectronics Conference (INEC)/Symposium on Nanoscience and Nanotechnology in China

作者： Chi, Yaqing Zhong, Haiqin Zhang, Chao Fang, Liang National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan 410073 China

ISBN: (纸本)9781424435449

Multi-island single electron transistor is an important kind of the single electron transistor, which is convenient to realize the controllable room temperature operation. A novel semi-empirical compact model for the Multi-island single electron transistor is proposed. The new approach combines the orthodox theory of the single electron tunneling through single coulomb island and a novel empirical analysis procedure for the chain of multi coulomb islands to solve the current of the whole multi-island single electron transistor. The tunneling rates are calculated based on the orthodox theory for the single electron tunneling. The tunneling currents representing the first splitted peaks in the coulomb oscillation curves are calculated according to the assumption that the currents through all the coulomb islands are equal to each other at the stable states, while the currents representing the other splitted peaks are constructed and merged together according to the empirical analysis. The model is verified by the traditional SET simulator SIMON and shows much faster calculation speed than SIMON. Therefore, the novel compact model is suitable for the large scale MISET circuit simulation.

关键词： Single Electron Transistor Coulomb Island Coulomb Oscillation Splitted Peak

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Impact of imprecise programming of memristor on building hardware neural network

Impact of imprecise programming of memristor on building har...

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2nd Annual Conference on Electrical and Control engineering, ICECE 2011

作者： Zhu, Xuan National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology ChangSha China

ISBN: (纸本)9781424481637

The application of memristor in building hardware neural network has accepted widespread interests, and may bring novel opportunities to neural computing. However, due to the limitation of programming precision, the conductance of memristor which represents stored information may deviate from theoretical value, and thus bring error to the neural computing results. In this paper, we analyze the impact of imprecise programming on building hardeware neural network through Monte Carlo simulation on feedback layer model. The results show that the fault-tolerance ability of neural network could well adapt to these errors, which further proves the potential of building neural networks using memristors. © 2011 IEEE.

关键词： Errors

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Survey of DHT topology construction techniques in virtual computing environments

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Science China(Information Sciences) 2011年第11期54卷 2221-2235页

作者： ZHANG YiMing 1,2,LU XiCheng 1,2 & LI DongSheng 1,21 National laboratory for parallel and distributed processing (PDL),Changsha 410073,China 2 school of computer,National University of Defense Technology,Changsha 410073,China 1. National Laboratory for Parallel and Distributed Processing (PDL) Changsha 410073 China2. School of Computer National University of Defense Technology Changsha 410073 China

The Internet-based virtual computing environment (iVCE) is a novel network computing *** characteristics of growth,autonomy,and diversity of Internet resources present great challenges to resource sharing in *** DHT overlay (DHT for short) technique has various advantages such as high scalability,low latency,and desirable availability,and is thus an important approach to realizing efficient resource *** construction is a key technique for structured overlays that realizes basic overlay functions including dynamic maintenance and message *** this paper,we first introduce the traditional techniques of DHT topology construction,focusing mainly on dynamic maintenance and message routing of typical DHTs,DHT indexing techniques for complex queries,and DHT grouping techniques for matching domain *** then present recent advances in DHT topology construction techniques in iVCE taking advantage of the characteristics of Internet ***,we discuss the future of DHT topology construction techniques.

关键词： virtual computing environments DHT overlays topology construction distributed indexing flexible routing

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Fault recovery based on parallel recomputing in transactional memory system

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2011 International Conference on Electric and Electronics, EEIC 2011

作者： Song, Wei Jia, Jia National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9783642217647

This paper addresses the issue of fault recovery in transactional memory, and proposes a method of fault recovery based on parallel recomputing in transactional memory system. This method utilizes the data-versioning mechanism of transactional memory system to avoid the extra cost of state saving, rolls back a single transaction to avoid wasting the computing time of the fault-free transactions, and adopts the parallel recomputing method to reduce the cost of fault recovery. This paper applies this method to OpenTM programs, and proposes the implementation method of parallel recomputing in OpenTM. At last, this paper tests the performance of this method through a test program. The experimental results show that, compared with the fault recovery method of rolling back a single transaction, the parallel recomputing method in transactional memory system can execute the fault recovery quickly and accurately and the method has a well scalability. © 2011 Springer-Verlag Berlin Heidelberg.

关键词： Fault tolerance

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A programming language approach to internet-based virtual environment computing

A programming language approach to internet-based virtual en...

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作者： Ji, Wang Shen, Rui Wang, Huai-Min National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

There is an increasing need to build scalable distributed systems over the Internet infrastructure. However, the development of distributed scalable applications suffers from lack of a wide accepted virtual computing environment. Users have to take great efforts on the management and sharing of the involved resources over Internet, whose characteristics are intrinsic growth, autonomy and diversity. To deal with this challenge, Internet-based Virtual Computing Environment (iVCE) is proposed and developed to serve as a platform for distributed scalable applications over the open infrastructure, whose kernel mechanisms are on-demand aggregation and autonomic collaboration of resources. In this paper, we present a programming language for iVCE named Owlet. Owlet conforms with the conceptual model of iVCE, and exposes the iVCE to application developers. As an interaction language based on peer-to-peer content-based publish/subscribe scheme, Owlet abstracts the Internet as an environment for the roles to interact, and uses roles to build a relatively stable view of resources for the on-demand resource aggregation. It provides language constructs to use 1) distributed event driven rules to describe interaction protocols among different roles, 2) conversations to correlate events and rules into a common context, and 3) resource pooling to do fault tolerance and load balancing among networked nodes. We have implemented an Owlet compiler and its runtime environment according to the architecture of iVCE, and built several Owlet applications, including a peer-to-peer file sharing application. Experimental results show that, with iVCE, the separation of resource aggregation logic and business logic significantly eases the process of building scalable distributed applications. © 2011 Springer Science+Business Media, LLC & Science Press, China.

关键词： Fault tolerance

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A task-mapping algorithm for performance simulation based on simulated annealing

A task-mapping algorithm for performance simulation based on...

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2011 International Conference on Computational and Information Sciences, ICCIS 2011

作者： Guo, Xiaowei Lin, Yufei Xu, Xinhai Zhang, Xin National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9780769545011

Nowadays, the scale of parallel computer systems is increasing, and simulation technology has become an important tool for performance prediction in the system development process. Task mapping approach is an important aspect affecting the performance of simulation. In this paper, in order to solve the task mapping problem in performance simulation, a task mapping algorithm based on simulated annealing is proposed, and we verified the correctness and effectiveness of the algorithm by experiments. Experimental results show that the algorithm has high efficiency, and can solve the large-scale problem with lower time cost. © 2011 IEEE.

关键词： Simulated annealing

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Error detection by redundant transaction in transactional memory system

Error detection by redundant transaction in transactional me...

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IEEE International Conference on Networking, Architecture and Storage

作者： Song, Wei Jia, Jia Peng, Yu-Xing National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769545097

This paper addresses the issue of error detection in transactional memory, and proposes a new method of error detection based on redundant transaction (EDRT). This method creates a transaction copy for every transaction, and executes both original transactions and transaction copies on adequate processor cores, and achieves error detection by comparing the execution results. EDRT utilizes the data-versioning mechanism of transactional memory to achieve the acquisition of an approximate minimum error detection comparing data set, and the acquisition is transparent and online. At last, this paper validates the EDRT through 5 test programs, including 4 SPLASH-2 benchmarks. The experimental results show that, the average error detecting cost is about 3.68% relative to the whole program, and it's only about 12.07% relative to the transaction parts of the program. © 2011 IEEE.

关键词： Fault tolerance

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An economical power management for high performance computers

An economical power management for high performance computer...

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2011 International Conference on Computational and Information Sciences, ICCIS 2011

作者： Wang, Huiquan Xu, Xinhai Zhou, Jing Zhou, Hao Wang, Guibin National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan 410073 China

ISBN: (纸本)9780769545011

The large amount of energy consumption of high performance computers represent significant financial cost. If we consider the specific situation of electricity price, a measure which makes the energy consumption the lowest is usually not the best on economy. This paper proposes an economical approach for designing a power management plan that reduces the assessment of energy consumption of high performance computers. By taking account of the electricity price in different periods during the day, we assign the workload to each period properly to make the electricity fee as low as possible. A simulation of the cases of a single task and multi-task demonstrates how our approach can be used. The results of the simulation show that our approach can save the electricity fee produced by high performance computers effectively. In the single task case, the proposed approach saves the electricity fee of 10.08% on average, and in the multi-task case the proportion of saved fee is 12.67%. © 2011 IEEE.

关键词： Power management

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Coordinate strip-mining and kernel fusion to lower power consumption on GPU

Coordinate strip-mining and kernel fusion to lower power con...

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作者： Wang, Guibin National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9783981080179

Although general purpose GPUs have relatively high computing capacity, they also introduce high power consumption compared with general purpose CPUs. Therefore low-power techniques targeted for GPUs will be one of the most hot topics in the future. On the other hand, in several application domains, users are unwilling to sacrifice performance to save power. In this paper, we propose an effective kernel fusion method to reduce the power consumption for GPUs without performance loss. Different from executing multiple kernels serially, the proposed method fuses several kernels into one larger kernel. Owing to the fact that most consecutive kernels in an application have data dependency and could not be fused directly, we split large kernel into multiple slices with strip-mining method, then fuse independent sliced kernels into one kernel. Based on the CUDA programming model, we propose three different kernel fusion implementations, with each one targeting for a special case. Based on the different strip-ming methods, we also propose two fusion mechanisms, which are called invariant-slice fusion and variant-slice fusion. The latter one could be better adapted to the requirements of the kernels to be fused. The experimental results validate that the proposed kernel fusion method could effectively reduce the power consumption for GPU. © 2011 EDAA.

关键词： Electric power utilization

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