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Using redundant threads for fault tolerance of OpenMP programs

Using redundant threads for fault tolerance of OpenMP progra...

引用

2010 International Conference in Information Science and Applications, ICISA 2010

作者： Fu, Hongyi Ding, Yan Key Laboratory of Science and Technology for National Defence of Parallel and Distributed Processing National University of Defence Tech. Changsha Hunan 410073 China School of Computer National University of Defence Tech. Changsha Hunan 410073 China

ISBN: (纸本)9781424459438

As the wide application of multi-core processor architecture in the domain of high performance computing, fault tolerance for shared memory parallel programs becomes a hot spot of research. For years, checkpointing has been the dominant fault tolerance technology in this field, and recently, many research works have been engaged with it. However, to those programs which deal with large amount of data, checkpointing may induce massive I/O transfer, which will adversely affect scalability. To deal with such a problem, this paper proposes a fault tolerance approach, making use of redundancy, for shared memory parallel programs. Our scheme avoids saving and restoring computational state during the program's execution, hence does not involve I/O operations, so presents explicit advantage over checkpointing in scalability. In this paper, we introduce our approach and the related compiler tool in detail, and give the experimental evaluation result. ©2010 IEEE.

关键词： Fault tolerance

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A Case Study of SWIM: Optimization of Memory Intensive Application on GPGPU

A Case Study of SWIM: Optimization of Memory Intensive Appli...

引用

International Symposium on parallel Architectures, Algorithms and Programming (PAAP)

作者： Wei Yi Yuhua Tang Guibin Wang Xudong Fang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

Recently, GPGPU has been adopted well in the High Performance Computing (HPC) field. The limited global memory bandwidth poses a great challenge to many GPGPU programmers trying to exploit parallelism within the CPU-GPU heterogeneous platform. In this paper, we choose SWIM, a typical memory intensive application from the SPEC OMP 2001 benchmark suite, for case study. We attempt to optimize the performance and energy consumption of the application utilizing different memory access mechanisms and present optimization methods including matrix transposition and kernel fusion. The experimental results on the Intel Core TM i920 CPU plus GeForce GTX 295 platform shows that, the proposed optimizing methods achieve a speedup of 8.7X over the original OpenMP program and reduce the energy consumption by 83% for the problem size of 2048*2048.

关键词： Instruction sets Kernel Bandwidth Graphics processing unit Memory management Energy consumption Central processing Unit

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Optimizing Adaptive Synchronization in parallel Simulators for Large-scale parallel Systems and Applications

Optimizing Adaptive Synchronization in Parallel Simulators f...

引用

International Conference on computer and Information Technology (CIT)

作者： Chuanfu Xu Yonggang Che Jianbin Fang Zhenghua Wang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

This paper addresses the optimization of parallel simulators for large-scale parallel systems and applications. Such simulators are often based on parallel discrete event simulation with conservative or optimistic protocols to synchronize the simulating processes. The paper considers how available future information about events and application behaviors can be efficiently extracted and further exploited to improve the performance of adaptive optimistic protocols. First, we extract information about future events and their dependencies in application traces to guide adaptive adjustments of time window in trace-driven parallel simulation. Second, we use information about application behaviors, specifically the iterative behavior found in many applications, to avoid the unnecessary adjustments of time window. These techniques are implemented in the BigSim simulator and tested by real-world and standard benchmark applications including Jacobi3D and HPL. The results show that our optimization approaches can reduce the execution times of simulation ranging from 11% up to 32%. Moreover, our methods are easy to implement and don't need to augment compilers or even modify the core codes of parallel simulators.

关键词： Adaptation model Computational modeling Schedules Optimization Protocols Synchronization Analytical models

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Towards Online Application Cache Behaviors Identification in CMPs

Towards Online Application Cache Behaviors Identification in...

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IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Xiaomin Jia Jiang Jiang Tianlei Zhao Shubo Qi Minxuan Zhang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

On chip multiprocessors (CMPs) platforms, multiple co-scheduled applications can severely degrade performance and quality of service (QoS) when they contend for last-level cache (LLC) resources. Whether an application will impose destructive interference on co-scheduled applications is largely dependent on its own inherent cache access behavior characteristics. In this work, we first present case studies that show how inter-application interferences result in undesirable performance in both shared and private cache based LLC designs. We then propose a new online approach for application cache behavior identification on the basis of detailed simulation and analysis with SPEC CPU2006 benchmarks. We demonstrate that our approach can more concisely identify application cache behaviors. Moreover, the proposed approach can be implemented directly in hardware to dynamically identify the application cache behaviors at runtime. Finally, we show with two case studies that how the proposed approach can be adopted by both shared and private based cache sharing mechanisms, i.e. cache partitioning algorithms (CPAs) and cache spilling techniques, for more concise cache resource management.

关键词： Benchmark testing Measurement Throughput Servers Interference Aerospace electronics Heuristic algorithms

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Effect of self and cross-coupling capacitance on stability diagram in a metallic double-dot device

Effect of self and cross-coupling capacitance on stability d...

引用

International Conference on Nanoscience and Nanotechnology, ICONN

作者： Bingcai Sui Liang Fang Yaqing Chi National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan China

We investigate the effect of self and cross-coupling capacitance on stability diagram in a metallic double-dot device by theory and method. In linear transport regime, cross-coupling capacitances affect the dimension of the honeycomb cell and the distance of two triple points, while self capacitances only slightly broaden the boundary of the cell and make two triple point closer. In nonlinear transport regime, cross-coupling capacitances stretch the current region and charge region in the mid-line direction, while self capacitances extend the region of current regions but not change the shape of the stability cells. Cross-coupling capacitances make stronger impact on the dimensions of stability diagram than self capacitance. But the self-capacitance must be included in the current calculation if its value can not be neglected with respect to the device parameters.

关键词： Stability analysis Tunneling Couplings Quantum capacitance Shape Junctions

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Communication delay analysis based on network calculus

Communication delay analysis based on network calculus

引用

International Conference on Software Technology and engineering (ICSTE)

作者： Yufei Lin Xinhai Xu Yisong Lin National Laboratory of Parallel and Distributed Processing Computer School National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781424486670

Network calculus is a promising theory for analyzing and modeling networks based on min-plus algebra. Using network calculus theory, we propose formulas of arrival curve and service curve for end-to-end communication, build the corresponding time model, and derive the communication delay formulas for two scenarios of the model respectively. Then we take fat tree topology, which is widely used in Infiniband interconnection, as an example to analyze the delay of one-to-all broadcast. This paper, as a groundwork, provides a new approach for the network researchers to delve communication delay in future researches.

关键词： Delay Calculus Bandwidth Algebra Computational modeling Topology Analytical models

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Power analysis and optimizations for GPU architecture using a power simulator

Power analysis and optimizations for GPU architecture using ...

引用

International Conference on Advanced computer Theory and engineering, ICACTE

作者： Guibin Wang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781424465392

As one of the most popular many-core architecture, GPUs have illustrated power in many non-graphic applications. Traditional general purpose computing systems tend to integrate GPU as the co-processor to accelerate parallel computing tasks. Meanwhile, GPUs also result in high power consumption, which accounts for a large proportion of the total system power consumption. In this paper, we mainly focus on the power analysis and optimizations for GPU architecture. The main contributions of this paper are: firstly, we establish a GPU power research platform, which is extended from an existing GPU simulator with several power models; secondly, we validate that, as the gap between shader core and memory speed becomes larger and larger, integrating more shader cores or enhancing running frequencies may not bring better performance, but results in higher energy consumption; thirdly, we show that traditional power optimization methods for CPUs, such as dynamic frequency scaling and concurrency-throttling, could be effectively applied on GPU architectures for better power efficiency, especially for memory-intensive applications.

关键词： Computational modeling Benchmark testing Graphics processing unit Arrays Analytical models Clocks Integrated circuit interconnections

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A multithreaded extension to the OR1200 processor

A multithreaded extension to the OR1200 processor

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International Conference on computer Science and Information Technology (CSIT)

作者： Kun Zeng Fudong Liu National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

Multithreading is a promising technique that widely used in general purpose processors to hide long latency events such as cache misses. This paper proposes an embedded processor design with multithreading support based on the OR1200 processor. The multithreaded OR1200 processor supports interleaved execution of four threads in a round-robin way. The hardware design is evaluated through RTL-simulation of the verilog code. Results show that the interleaved execution of multiple threads can tolerate the memory latency effectively and an average speed-up of 1.16 can be achieved.

关键词： Registers Artificial neural networks Field-flow fractionation Reduced instruction set computing

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Sim-spm: A SimpleScalar-Based Simulator for Multi-level SPM Memory Hierarchy Architecture

Sim-spm: A SimpleScalar-Based Simulator for Multi-level SPM ...

引用

IEEE International Conference on High Performance Computing and Communications (HPCC)

作者： Xiaoguang Ren Yuhua Tang Tao Tang Sen Ye Huiquan Wang Jing Zhou National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

As a fast on-chip SRAM managed by software (the application and/or compiler), Scratchpad Memory (SPM) is widely used in many fields. This paper presents a Simple Scalar-based multi-level SPM memory hierarchy architecture simulator Sim-spm. We simulate the hardware of the multi-level SPM memory hierarchy successfully by extending Sim-outorder, which is an out-of-order simulator from Simple Scalar. Through the simulating memory method, the simulation framework of the multi-level SPM memory hierarchy has been built under the existing ISA (Instruction Set Architecture), which largely reduces the requirement to modify the existing compiler. The experimental results show that Sim-spm can accurately simulate the running state of the processor with a multi-level SPM memory hierarchy architecture, and it has a good prospect for the research of multi-level SPM memory hierarchy architecture.

关键词： Kernel Random access memory Libraries Memory management Memory architecture

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Communication time models on fat-tree networks

Communication time models on fat-tree networks

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International Conference on Advanced computer Theory and engineering, ICACTE

作者： Yufei Lin Xinhai Xu Yisong Lin National Laboratory of Parallel and Distributed Processing Computer School National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781424465392;9781424465422

With the growth of supercomputer's scale, the communication time during executing is increasing. This phenomenon arouses the architecture researchers' interests. In this paper, based on the fat-tree topology, which is widely used in Infiniband, we present an one-to-all broadcast communication time model. After classifying applications into two kinds, we establish the ideal model and the bandwidth-limited model on the exponential-capacity binary fat-trees for the two kinds of applications. Through analyzing the models, we get the curves which describe the relationship between the communication time and the processor number. The conclusions we get in this paper can help system designers make better system design.

关键词： World Wide Web

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