检索结果-内蒙古大学图书馆

4th International Conference on Computational Intelligence and Communication Networks, CICN 2012

作者： Xu, Xinhai Lin, Yufei National Laboratory for Parallel and Distributed Processing Computer School National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781467329811

Nowadays, with the growth of the performance, the reliability problem of supercomputers becomes more and more serious. In order to complete an application with small fault recovery overhead, Checkpoint/Restart(C/R) methods are widely used. So far, the mainstream C/R methods are either based on Fail-Stop fault model or making the system(or program) do error detection before storing checkpoints, so they can ensure the correctness of every checkpoint. However, the faults occurring in the systems in real world are more accordant with the Byzantine fault model, and in order to pursue the higher practical performance, neither the system nor the program implements any fault detection mechanism. Consequently, there may be errors in the checkpoints. This paper studies the checkpoint selection problem that which checkpoint should be selected as the object of rolling back after system occurring failure, based on Byzantine fault model. We design a framework of checkpoint selection, and then, based on it, propose three checkpoint selection strategies: conservative strategy, aggressive strategy and statistical strategy. The simulation results show that: the conservative strategy shows its superiority when the error latent period is long, while the aggressive strategy behaves oppositely, the statistical strategy has a stable efficiency, only 50% more overhead compared to the ideal checkpoint selection when the checkpoint period is the half of mean time between faults. © 2012 IEEE.

关键词： Fault tolerance

来源：评论

学校读者我要写书评

暂无评论

SMP-SIM: An event-driven performance simulator for SMP

SMP-SIM: An event-driven performance simulator for SMP

引用

2012 International Conference on Systems and Informatics, ICSAI 2012

作者： Zhang, Xin Tang, Yuhua Lin, Yufei Xu, Xinhai Guo, Xiaowei Ren, Xiaoguang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781467301992

Performance prediction for the high performance computer system is of great importance for designing, implementing, and optimizing system. As a widely used technique for predicting performance, simulation method attracts more and more attention from the research community. Based on analyzing the problems in the current performance simulation techniques, we present a key idea of the performance simulator for SMP system based on event-driven. We propose the framework of SMP-SIM and implement it based on MPICH2. The simulation results show that, our simulation technique has the advantages of high accuracy and simulation performance. © 2012 IEEE.

关键词： Forecasting

来源：评论

学校读者我要写书评

暂无评论

CANSE: A churn adaptive approach to network size estimation

CANSE: A churn adaptive approach to network size estimation

引用

16th IEEE International Conference on parallel and distributed Systems, ICPADS 2010

作者： Ma, Xing-Kong Wang, Yi-Jie Zheng, Zhong National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9780769543079

Network size is one of the fundamental information of distributed applications. The approach to estimate network size must feature both high accuracy and robustness in order to adapt to the dynamic environment in different topologies. However, existing approaches fail to guarantee accuracy and robustness simultaneously in dynamic topologies due to the randomness of nodes sampled. In this paper, we propose a churn adaptive approach to network size estimation - CANSE, which collects closest nodes in identification to each node's identification by sampling nodes periodically. Each node collects closest identifications by two schemes. One scheme is sampling random nodes from random walks along the topology. The other one is exchanging the closest identifications with other nodes. Finally, each node calculates the average spacing of the closest identifications collected to estimate network size. Compared with existing approaches, extensive experiments show that CANSE provides accurate estimation values quickly in various dynamic topologies. © 2010 IEEE.

关键词： Topology

来源：评论

学校读者我要写书评

暂无评论

Program optimization of array-intensive SPEC2k benchmarks on multithreaded GPU using CUDA and brook+

Program optimization of array-intensive SPEC2k benchmarks on...

引用

15th International Conference on parallel and distributed Systems, ICPADS '09

作者： Wang, Guibin Tang, Tao Fang, Xudong Ren, Xiaoguang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9780769539003

Graphic processing Unit (GPU), with many lightweight data-parallel cores, can provide substantial parallel computing power to accelerate several general purpose applications. Both the AMD and NVIDIA corps provide their specific high performance GPUs and software platforms. As the floating-point computing capacity increases continually, the problem of "memory-wall" becomes more serious, especially for array-intensive applications. In this paper, we optimize and implement two SPEC2k benchmarks mgrid and swim on multithreaded GPU using CUDA and Brook+. In order to reduce the pressure on off-hip memory, we make use of data locality in multi-level memory hierarchies and hide long memory access latency via double-buffers. To balance inter-thread parallelism and intra-hread locality, we further tune thread granularity for each kernel and empirically study the best equilibrium point for this problem. Flow control instruction can significantly impact the effective instruction throughput. Oriented to this problem, we introduce a diverge elimination technology to convert condition expression into computing operation. Through all the optimizations, we gain the speedup of 10x-34x to the CPU implementation on the GPUs of AMD and NVIDIA respectively. Finally, we summarize and compares the GPUs from AMD and NVIDIA in hardware and software. © 2009 IEEE.

关键词： Graphics processing unit

来源：评论

学校读者我要写书评

暂无评论

Power analysis and optimizations for GPU architecture using a power simulator

Power analysis and optimizations for GPU architecture using ...

引用

2010 3rd International Conference on Advanced computer Theory and Engineering, ICACTE 2010

作者： Wang, Guibin National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781424465408

As one of the most popular many-core architecture, GPUs have illustrated power in many non-graphic applications. Traditional general purpose computing systems tend to integrate GPU as the co-processor to accelerate parallel computing tasks. Meanwhile, GPUs also result in high power consumption, which accounts for a large proportion of the total system power consumption. In this paper, we mainly focus on the power analysis and optimizations for GPU architecture. The main contributions of this paper are: firstly, we establish a GPU power reserach platform, which is extended from an existing GPU simulator with several power models;secondly, we validate that, as the gap between shader core and memory speed becomes larger and larger, integrating more shader cores or enhancing running frequencies may not bring better performance, but results in higher energy consumption;thirdly, we show that traditional power optimization methods for CPUs, such as dynamic frequency scaling and concurrencythrottling, could be effectively applied on GPU architectures for better power efficiency, especially for memory-intensive applications. © 2010 IEEE.

关键词： Simulators

来源：评论

学校读者我要写书评

暂无评论

Invalid pointer dereferences detection for CPS software based on extended pointer structures

Invalid pointer dereferences detection for CPS software base...

引用

2012 IEEE 6th International Conference on Software Security and Reliability Companion, SERE-C 2012

作者： Dong, Longming Dong, Wei Chen, Liqian National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769547435

Invalid pointer dereferences, such as null pointer dereferences, dangling pointer dereferences and double frees, are a prevalent source of software bugs in CPS software, due to flexible dereferencing pointers along various pointer fields. Existing tools have high overhead or are incomplete, thereby limiting their efficiency in checking the kind of CPS software with shared and mutable memory. In this paper, we present a novel extended pointer structure for detecting all invalid pointer dereferences in this kind of CPS software. We propose an invalid pointer dereferences detection algorithm based on the uniform transformation of abstract heap states. Experimental evaluation about a set of large C benchmark programs shows that the proposed approach is sufficiently efficient in detecting invalid pointer dereferences of CPS software with shared and mutable memory. © 2012 IEEE.

关键词： Program debugging

来源：评论

学校读者我要写书评

暂无评论

Error detection by redundant transaction in transactional memory system

Error detection by redundant transaction in transactional me...

引用

IEEE International Conference on Networking, Architecture and Storage

作者： Song, Wei Jia, Jia Peng, Yu-Xing National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha 410073 China

ISBN: (纸本)9780769545097

This paper addresses the issue of error detection in transactional memory, and proposes a new method of error detection based on redundant transaction (EDRT). This method creates a transaction copy for every transaction, and executes both original transactions and transaction copies on adequate processor cores, and achieves error detection by comparing the execution results. EDRT utilizes the data-versioning mechanism of transactional memory to achieve the acquisition of an approximate minimum error detection comparing data set, and the acquisition is transparent and online. At last, this paper validates the EDRT through 5 test programs, including 4 SPLASH-2 benchmarks. The experimental results show that, the average error detecting cost is about 3.68% relative to the whole program, and it's only about 12.07% relative to the transaction parts of the program. © 2011 IEEE.

关键词： Fault tolerance

来源：评论

学校读者我要写书评

暂无评论

Untrusted Hardware Causes Double-Fetch Problems in the I/O Memory

引用

Journal of computer science & technology 2018年第3期33卷 587-602页

作者： Kai Lu Peng-Fei Wang Gen Li Xu Zhou College of Computer National University of Defense Technology Changsha 410073 China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha 410073 China Collaborative Innovation Center of High-Performance Computing National University of Defense Technology Changsha 410073 China

The double fetch problem occurs when the data is maliciously changed between two kernel reads of the supposedly same data, which can cause serious security problems in the kernel. Previous research focused on the double fetches between the kernel and user applications. In this paper, we present the first dedicated study of the double fetch problem between the kernel and peripheral devices （aka. the hardware double fetch）. Operating systems communicate with peripheral devices by reading from and writing to the device mapped I/O （input and output） memory. Owing to the lack of effective validation of the attached hardware, compromised hardware could flip the data between two reads of the same I/O memory address, causing a double fetch problem. We propose a static pattern-matching approach to identify the hardware double fetches from the Linux kernel. Our approach can analyze the entire kernel without relying on the corresponding hardware. The results are categorized and each category is analyzed using case studies to discuss the possibility of causing bugs. We also find four previously unknown double-fetch vulnerabilities, which have been confirmed and fixed after reporting them to the maintainers.

关键词： hardware double fetch double-fetch bug I/O memory peripheral device double-fetch vulnerability

来源：评论

学校读者我要写书评

暂无评论

A distributed class-incremental learning method based on neural network parameter fusion 21

A distributed class-incremental learning method based on neu...

引用

21st IEEE International Conference on High Performance Computing and Communications, 17th IEEE International Conference on Smart City and 5th IEEE International Conference on Data science and Systems, HPCC/SmartCity/DSS 2019

作者： Guan, Hongtao Wang, Yijie Ma, Xingkong Li, Yongmou National Laboratory for Parallel and Distributed Processing College of Computer Science and Technology National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781728120584

Class-incremental learning has received considerable attention due to the better adaptability to constantly changing characteristic of online learning. The neural network is suitable for class-incremental learning because of batch training style and fine-tuning. However, as the rapid growth of data centers and data category, data isolated island problem presents a new challenge to the current machine learning model: how to provide an accurate training method in a distributed and incremental manner. Existing solutions cannot adapt to incremental classes without aggregating data. In this paper, we propose a distributed class-incremental learning framework, called DCIL, which iteratively updates new class parameters and fixes existing class parameters to achieve high training accuracy. Especially, we propose MF, a parameter fusion method to integrate the parameters of multi-nodes into a new global parameter. In order to match the requirements of identical columns corresponding to the known classes, we propose a single node class-incremental learning, called SCIL. To evaluate the performance of DCIL, we conduct experiments on 5 datasets under various parameter settings on both 2 and 4 nodes distributed scenarios. Extensive experiments confirm that DCIL outperform the general baselines and achieve classification accuracy closes to the method of data aggregating. © 2019 IEEE.

关键词： Iterative methods

来源：评论

学校读者我要写书评

暂无评论

DFTracker: detecting double-fetch bugs by multi-taint parallel tracking

引用

Frontiers of computer science 2019年第2期13卷 247-263页

作者： Pengfei WANG Kai LU Gen LI Xu ZHOU Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha 410073 China College of Computer National University of Defense Technology Changsha 410073 China Collaborative Innovation Center of High Performance Computing National University of Defense Technology Changsha 410073 China

A race condition is a common trigger for concurrency bugs. As a special case, a race condition can also occur across the kernel and user space causing a doublefetch bug, which is a field that has received little research attention. In our work, we first analyzed real-world doublefetch bug cases and extracted two specific patterns for doublefetch bugs. Based on these patter ns, we proposed an approach of multi-taint parallel tracking to detect double-fetch bugs. We also implemented a prototype called DFTracker (doublefetch bug tracker), and we evaluated it with our test suite. Our experiments demonstrated that it could effectively find all the double-fetch bugs in the test suite including eight realworld cases with no false negatives and minor false positives. In addition, we tested it on Linux kernel and found a new double-fetch bug. The execution overhead is approximately 2x for single-file cases and approximately 9x for the whole kernel test, which is acceptable. To the best of the authors1 knowledge, this work is the first to introduce multi-taint parallel tracking to double-fetch bug detection—an innovative method that is specific to double-fetch bug features—and has better path coverage as well as lower runtime overhead than the widely used dynamic approaches.

关键词： multi-taint parallel tracking double fetch race condition between kernel and user time of check to time of use real-world case analysis Clang Static Analyzer

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：