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AutoMal: Automatic clustering and signature generation for malwares based on the network flow

Security and Communication Networks 2015年第10期8卷 1845-1854页

作者： Hao, Sun Wang, Wen Lu, Huabiao Ren, Peige School of Computer National University of Defense Technology Changsha China National Key Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha China

The volume of malwares is growing at an exponential speed nowadays. This huge growth makes it extremely hard to analyse malware manually. Most existing signatures extracting methods are based on string signatures, and string matching is not accurate and time consuming. Therefore, this paper presents AutoMal, a system for automatically extracting signatures from large-scale malwares. Firstly, the system proposes to represent the network flows by using feature hashing, which can dramatically reduce the high-dimensional feature spaces that are general in malware analysis. Then, we design a clustering and median filtering method to classify the malware vectors into different types. Finally, it introduces the signature generation algorithm based on Bayesian method. The system can extract both the byte signature and the hash signature of malwares from its network flow with low false positive and zero false negative. Our evaluation shows that AutoMal can generate strongly noise-resisted signatures that exactly depict the characteristics of malware. © 2014 John Wiley & Sons, Ltd.

关键词： Malware

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Experimental verification of the parasitic bipolar amplification effect in PMOS single event transients

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Chinese Physics B 2014年第7期23卷 775-779页

作者：何益百陈书明 College of Computer National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology

The contribution of parasitic bipolar amplification to SETs is experimentally verified using two P-hit target chains in the normal layout and in the special layout. For PMOSs in the normal layout, the single-event charge collection is composed of diffusion, drift, and the parasitic bipolar effect, while for PMOSs in the special layout, the parasitic bipolar junction transistor cannot turn on. Heavy ion experimental results show that PMOSs without parasitic bipolar amplification have a 21.4% decrease in the average SET pulse width and roughly a 40.2% reduction in the SET cross-section.

关键词： single event effect single event transient parasitic bipolar amplification heavy ion experiments

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Design, Implementation and Evaluation of an Application-Layer Virtualized Network

Design, Implementation and Evaluation of an Application-Laye...

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2015 IEEE Symposium on Service-Oriented System Engineering

作者： Yiming Zhang Dongsheng Li Yijie Wang Zhigang Sun Feng Zhao Jinshu Su National University of Defense Technology Changsha Hunan CN School of Computer National Laboratory for Parallel and Distributed Processing (PDL) Changsha China

The performance of virtualized networks is critical to cloud applications. The "distributed line graphs" (DLG) are a universal technique for designing network topologies based on arbitrary regular graphs. In this paper we implement a prototype (C library) for a DLG-enabled network (called DLG-Kautz), as an application-layer virtualized network service. The effectiveness of our design and implementation is demonstrated through prototype evaluations.

关键词： Routing Message systems Ports (computers) Servers Payloads Prototypes Libraries

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Implementation of an Accurate and Efficient Compensated DGEMM for 64-bit ARMv8 Multi-Core Processors

Implementation of an Accurate and Efficient Compensated DGEM...

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International Conference on parallel and distributed Systems (ICPADS)

作者： Hao Jiang Feng Wang Kuan Li Canqun Yang Kejia Zhao Chun Huang College of Computer Science National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9781467386692

This paper presents an implementation of an accurate and efficient compensated Double-precision General Matrix Multiplication (DGEMM) based on OpenBLAS for 64-bit ARMv8 multi-core processors. Due to cancellation phenomena in floating point arithmetic, the results of DGEMM may not be as accurate as expected. In order to increase the accuracy of DGEMM, we compensate the error introduced by its dot product kernel (GEBP) by applying an error-free transformation to rewrite the kernel in assembly language. We optimize the computations in the inner kernel through exploiting loop unrolling, instruction scheduling and software-implemented register rotation to exploit instruction level parallelism (ILP). We also conduct a priori error analysis of the derived CompDGEMM. Our compensated DGEMM is as accurate as the existing quadruple precision GEMM using MBLAS, but is up to 6.4x faster. Our parallel implementation achieves good performance and scalability under varying thread counts across a range of matrix sizes evaluated.

关键词： Multicore processing Kernel Registers Libraries Error analysis Algorithm design and analysis

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A low-latency fine-grained dynamic shared cache management scheme for chip multi-processor

A low-latency fine-grained dynamic shared cache management s...

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IEEE International Conference on Performance, Computing and Communications (IPCCC)

作者： Jinbo Xu Weixia Xu Zhengbin Pang College of Computer National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

In order to utilize the shared last-level cache (LLC) in chip multi-processors (CMP) more efficiently, the partitioning of LLC resources among all cores should have the characteristics of low-latency for access, fine granularity for migration and simple hardware complexity for implementation. This paper proposes a dynamic LLC management scheme to achieve these goals. The proposed scheme migrates cache resources among different cores at the granularity of cache blocks, instead of ways. The quantity of victim cache blocks that each victim core can migrate to other target cores are related to an eviction probability, which are calculated according to the performance goal. Then the victim cache blocks for a target core is chosen from the nearest victim core who has non-zero eviction probability by introducing innovate E-Table structure in CMP. The eviction probabilities are updated periodically. With the help of E-Tables, the proposal achieves low-latency accesses by always keeping the required cache blocks near to the target cores. And fine granularity is guaranteed by maintaining an eviction probability for each core. In addition, only little additional hardware changes to traditional cache structure is required. Simulation results suggest significant performance improvements from 6.8% to 22.7% over related works.

关键词： Hardware Resource management Probability distribution Proposals Complexity theory Simulation

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Poster: Segmentation Based Online Performance Problem Diagnosis

Poster: Segmentation Based Online Performance Problem Diagno...

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International Conference on Software Engineering (ICSE)

作者： Jingwen Zhou Zhenbang Chen Ji Wang College of Computer National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9781479919352

Currently, the performance problems of software systems gets more and more attentions. Among various diagnosis methods based on system traces, principal component analysis (PCA) based methods are widely used due to the high accuracy of the diagnosis results and requiring no specific domain knowledge. However, according to our experiments, we have validated several shortcomings existed in PCA-based methods, including requiring traces with a same call sequence, inefficiency when the traces are long, and missing performance problems. To cope with these issues, we introduce a segmentation based online diagnosis method in this poster.

关键词： Principal component analysis Software systems Accuracy Measurement Monitoring computer architecture Conferences

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MPISE: Symbolic Execution of MPI Programs

MPISE: Symbolic Execution of MPI Programs

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IEEE International Symposim on High Assurance Systems Engineering

作者： Xianjin Fu Zhenbang Chen Yufeng Zhang Chun Huang Wei Dong Ji Wang College of Computer National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

ISBN: (纸本)9781479981120

Message Passing Interfaces (MPI) plays an important role in parallel computing. Many parallel applications are implemented as MPI programs. The existing methods of bug detection for MPI programs have the shortage of providing both input and non-determinism coverage, leading to missed bugs. In this paper, we employ symbolic execution to ensure the input coverage, and propose an on-the-fly schedule algorithm to reduce the interleaving explorations for non-determinism coverage, while ensuring the soundness and completeness. We have implemented our approach as a tool, called MPISE, which can automatically detect the deadlock and runtime bugs in MPI programs. The results of the experiments on benchmark programs and real world MPI programs indicate that MPISE finds bugs effectively and efficiently. In addition, our tool also provides diagnostic information and replay mechanism to help understand bugs.

关键词： computer bugs System recovery Switches Synchronization Runtime Testing Scheduling

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Design and Implementation of a Highly Efficient DGEMM for 64-Bit ARMv8 Multi-core Processors

Design and Implementation of a Highly Efficient DGEMM for 64...

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International Conference on parallel processing (ICPP)

作者： Feng Wang Hao Jiang Ke Zuo Xing Su Jingling Xue Canqun Yang School of Computer Science National University of Defense Technology Changsha China School of Computer Science and Engineering University of New South Wales NSW Australia Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China

This paper presents the design and implementation of a highly efficient Double-precision General Matrix Multiplication (DGEMM) based on Open BLAS for 64-bit ARMv8 eight-core processors. We adopt a theory-guided approach by first developing a performance model for this architecture and then using it to guide our exploration. The key enabler for a highly efficient DGEMM is a highly-optimized inner kernel GEBP developed in assembly language. We have obtained GEBP by (1) maximizing its compute-to-memory access ratios across all levels of the memory hierarchy in the ARMv8 architecture with its performance-critical block sizes being determined analytically, and (2) optimizing its computations through exploiting loop unrolling, instruction scheduling and software-implemented register rotation and taking advantage of A64 instructions to support efficient FMA operations, data transfers and prefetching. We have compared our DGEMM implemented in Open BLAS with another implemented in ATLAS (also in terms of a highly-optimized GEBP in assembly). Our implementation outperforms the one in ALTAS by improving the peak performance (efficiency) of DGEMM from 3.88 Gflops (80.9%) to 4.19 Gflops (87.2%) on one core and from 30.4 Gflops (79.2%) to 32.7 Gflops (85.3%) on eight cores. These results translate into substantial performance (efficiency) improvements by 7.79% on one core and 7.70% on eight cores. In addition, the efficiency of our implementation on one core is very close to the theoretical upper bound 91.5% obtained from micro-benchmarking. Our parallel implementation achieves good performance and scalability under varying thread counts across a range of matrix sizes evaluated.

关键词： Registers Kernel Computational modeling Program processors Assembly Memory management

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Accelerating FDTD simulation of microwave pulse coupling into narrow slots on the Intel MIC architecture

Accelerating FDTD simulation of microwave pulse coupling int...

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IEEE Pacific Rim Conference on Communications, computers and Signal processing

作者： Qinglin Wang Jie Liu Xiantao Cui Guitao Fu Chunye Gong Zuocheng Xing School of Computer Science National University of Defense Technology Changsha China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha China Beijing Satellite Navigation Center Beijing China

ISBN: (纸本)9781467377898

The coupling of microwaves into apertures plays an important part in many electromagnetic physics and engineering fields. When the width of apertures is very small, Finite Difference Time Domain (FDTD) simulation of the coupling is very time-consuming. As a many-core architecture, the Intel's Many Integrated Core (MIC) architecture owns 512-bit vector units and more than 200 threads. In this paper, we parallelize FDTD simulation of microwave pulse coupling into narrow slots on the Intel MIC architecture. In the implementation, the parallel programming model OpenMP is used to exploit thread parallelism while loop unrolling and SIMD intrinsic functions are utilized to accomplish vectorization. Compared with the serial version on Intel Xeon E5-2670 CPU, the implementation on the MIC coprocessor including 57 cores obtains a speedup of 11.57 times. The experiment results also demonstrate that the parallelization has good scalability in performance. Additionally, how binding relationship between OpenMP threads and hardware threads in MIC influences performance is also reported.

关键词： Microwave integrated circuits Finite difference methods Time-domain analysis Chlorine Hardware

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A Novel Run-time Load Balancing Method for MapReduce

A Novel Run-time Load Balancing Method for MapReduce

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International Conference on computer science and Network technology

作者： Zhihong Liu Yaping Liu Baosheng Wang Zhenghu Gong College of Computer National University of Defense Technology Changsha Hunan China Science and Technology on Parallel and Distributed Processing Laboratory National University of Defense Technology Changsha Hunan China

ISBN: (纸本)9781467381741

In recent years, many companies are embracing the Hadoop MapReduce system for large-data processing with completion time constrains. However, exiting Hadoop schedulers still suffer from the reducer load imbalancing problem. In this paper, we present a novel run-time load balancing method for MapReduce. Our approach predicts the workload of each reduce task at run-time, and assigns the reduce tasks to specified machines based on the estimated workload of reduce tasks dynamically. Therefore, our approach can achieve load balance among machines. The experimental results show that our approach achieves high accuracy while predicting the workload of reduce tasks, and improves the job completion time by up to 23.15%.

关键词： MapReduce load balancing task scheduling Load balancing TASK SCHEDULING Completion time Runtime Workload Religious Missions

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