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Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)

作者： Anwen Huang Jun Gao Chaochao Feng Minxuan Zhang Key Laboratory of Science and Technology of National Defense of Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha China

It is of great significance to optimize the design of on-chip memory system for improving the performance of multi-core processor. This paper describes the organization of on-chip memory hierarchy in UltraSPARC T2, analyzes the procedure of dealing with the memory access request from multi-core processor in detail. To get the basic parameters of timing characteristic and area consumption, the primary element of on-chip memory system is simulated by ModelSim and synthesized by Synopsys Design Complier with 90 nm standard cell library. Aimed at the potential limiting factor of improving the performance of memory hierarchy, corresponding optimization techniques of critical elements in memory system are explored finally.

关键词： System-on-a-chip Elliptic curve cryptography Hardware Costs Algorithm design and analysis Random access memory Clocks Registers Elliptic curves Protection

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A Two-Phase Mapping Method for parallel Applications Simulation

A Two-Phase Mapping Method for Parallel Applications Simulat...

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International Conference on Computational Intelligence and Software Engineering (CiSE)

作者： Jianbin Fang Chuanfu Xu Yonggang Che Yufen Weng Zhenghua Wang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

Efficient mapping of logical processes to physical processes is one of key technologies to accelerate parallel performance simulation. Aiming at minimizing the communications between SMP nodes and between host physical processes, this paper presents a novel method named TPsmp-LP 3 M. It automatically extracts communication pattern of logical processes from trace and then generates a two-phase mapping from logical processes to SMP clusters. Experimental results show that TPsmp-LP 3 M can outperform the regular mapping method by up to 20.2%.

关键词： Computational modeling computer simulation Bandwidth Predictive models Discrete event simulation Concurrent computing parallel processing Application software Laboratories distributed processing

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iRank: Supporting Proximity Ranking for Peer-to-Peer Applications

iRank: Supporting Proximity Ranking for Peer-to-Peer Applica...

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International Conference on parallel and distributed Systems (ICPADS)

作者： Yongquan Fu Yijie Wang National Key Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology China

Proximity ranking according to end-to-end network distances (e.g., Round-Trip Time, RTT) can reveal detailed proximity information, which is important in network management and performance diagnosis in distributed systems. However, to the best of our knowledge, there has been no similar work on this subject in the P2P computing field. We present a distributed rating method iRank, that enables proximity rankings by providing discrete ratings in a distributed manner. It formulates the proximity ranking as a rating problem that faithfully captures the proximity based on noisy distance measurements scalably and practically. The primary challenge in inferring proximity rankings is enforcing distributed ratings with complex rating policies. Our solution is based on reconstructing ratings by decomposing a centralized rating method Maximum Margin Matrix Factorization (MMMF) into independent sub-problems, that can be efficiently solved in a decentralized manner. By relaxing the dependence on infrastructure nodes that are a single point of failure and limit scalability, iRank can gracefully handle network churns. Through real network latency data sets, we demonstrate that iRank can predict ratings with low distortion, which are smaller than 20 percentage worse than the centralized method, in the context of synthetic complex rating policies.

关键词： Peer to peer computing distributed computing computer networks Network servers Application software Laboratories distributed processing Concurrent computing computer network management Conference management

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Towards efficient mapping in large-scale trace-driven parallel performance simulation

Towards efficient mapping in large-scale trace-driven parall...

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IEEE Youth Conference on Information, Computing and Telecommunication, YC-ICT

作者： Chuanfu Xu Yonggang Che Jianbin Fang Zhenghua Wang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

In parallel performance simulation of parallel systems, a large amount of logic processes (LP) must be mapped to relatively small number of physical elements (PE). Previous researches have shown that different mapping schemes could result in significant variation in the whole parallel simulation cost. In this paper, we propose, implement, and evaluate a minimum communication-guided mapping (MiniCoM) scheme for large-scale trace-driven parallel performance simulation. Guided by extracted information about interactions among LPs from previously generated traces, MiniCoM can map some most frequently interacted LPs to the same PE while trying to keep load balance between PEs. The mapping aims to minimize realistic communications among PEs which may run on different nodes of host systems with large inter-node latency. We use BigSim simulator and two target programs to evaluate MiniCoM. Our results show that MiniCoM is more efficient than blocked mapping adopted by BigSim: it can reduce the total parallel simulation runtime by up to 49%.

关键词： Large-scale systems Computational modeling parallel processing Discrete event simulation computer simulation Concurrent computing Data mining Laboratories distributed processing distributed computing

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Simulation and analysis of single-electron transistors with 1-dimension multiple islands

Simulation and analysis of single-electron transistors with ...

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IEEE Conference on Nanotechnology

作者： Bingcai Sui Yaqing Chi Hailiang Zhou Chao Zhang Liang Fang National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Hunan China

ISBN: (纸本)9781424448326

Single-electronic transistors (SETs) are considered as the attractive candidates for post-COMS VLSI due to their ultra-small size and low power consumption. Because SETs with single island can not work at room temperature normally, more and more researchers begin to make research on the SETs with 1-dimension multi-islands. Based on the Monte Carlo (MC) and stable diagram method, the critical problems during simulating and analyzing the SETs with multi-islands are investigated, e.g. capacitance matrix, potential of the islands, the free energy and so on. Meanwhile, double-island SET is simulated and analyzed as an example of SETs with 1-D muti-islands in detail. For the first time, 3-D stable diagram is obtained, and some new phenomena are analyzed in the paper. And through analyzing the result it's shown that although SETs with 1-D muti-islands is more useful and powerful than SETs with single island, there inevitably exists many effects because of the coupling energy between the islands.

关键词： Analytical models Single electron transistors Tunneling Carbon nanotubes Capacitance Voltage Energy consumption Capacitors Very large scale integration Temperature

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HyperSpring: Accurate and Stable Latency Estimation in the Hyperbolic Space

HyperSpring: Accurate and Stable Latency Estimation in the H...

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International Conference on parallel and distributed Systems (ICPADS)

作者： Yongquan Fu Yijie Wang National Key Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology China

Predicting network latencies between Internet hosts can efficiently support large-scale Internet applications, e.g., file sharing service and the overlay construction. Several study use the hyperbolic space to model the Internet dense-core and many-tendril structure. However, existing hyperbolic space based embedding approaches are not designed for accurate latency estimation in the distributed context. We present HyperSpring, which estimates latency by modelling a mass spring system in the hyperbolic similar with Vivaldi. HyperSpring adopts coordinate initialization to speed up the convergence of coordinate computation, uses multiple-round symmetric updates to escape from bad local minima, and stabilizes coordinates by compensating RTT measurements to reduce the coordinate drifts. Evaluation results based on a network trace of 226 PlanetLab nodes indicate that, compared to Euclidean-space based Vivaldi, hyperspring provides performance improvements for most nodes, and incurs slightly higher distortions for a small number of nodes.

关键词： Delay IP networks Web and internet services Large-scale systems Peer to peer computing Springs Convergence Coordinate measuring machines Distortion measurement Extraterrestrial measurements

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Program Optimization of Array-Intensive SPEC2k Benchmarks on Multithreaded GPU Using CUDA and Brook+

Program Optimization of Array-Intensive SPEC2k Benchmarks on...

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International Conference on parallel and distributed Systems (ICPADS)

作者： Guibin Wang Tao Tang Xudong Fang Xiaoguang Ren National Laboratory of Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

Graphic processing Unit (GPU), with many light-weight data-parallel cores, can provide substantial parallel computing power to accelerate several general purpose applications. Both the AMD and NVIDIA corps provide their specific high performance GPUs and software platforms. As the floating-point computing capacity increases continually, the problem of ``memory-wall'' becomes more serious, especially for array-intensive applications. In this paper, we optimize and implement two SPEC2k benchmarks mgrid and swim on multithreaded GPU using CUDA and Brook+. In order to reduce the pressure on off-chip memory, we make use of data locality in multi-level memory hierarchies and hide long memory access latency via double-buffers. To balance inter-thread parallelism and intra-thread locality, we further tune thread granularity for each kernel and empirically study the best equilibrium point for this problem. Flow control instruction can significantly impact the effective instruction throughput. Oriented to this problem, we introduce a diverge elimination technology to convert condition expression into computing operation. Through all the optimizations, we gain the speedup of 10×-34× to the CPU implementation on the GPUs of AMD and NVIDIA respectively. Finally, we summarize and compares the GPUs from AMD and NVIDIA in hardware and software.

关键词： parallel processing Application software Graphics Acceleration Software performance Delay Yarn Kernel Throughput Central processing Unit

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Program Optimization of Stencil Based Application on the GPU-Accelerated System

Program Optimization of Stencil Based Application on the GPU...

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International Symposium on parallel and distributed processing with Applications, ISPA

作者： Guibin Wang Xuejun Yang Ying Zhang Tao Tang XuDong Fang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

Graphic processing Unit (GPU), with many light-weight data-parallel cores, can provide substantial parallel computational power to accelerate general purpose applications. But the powerful computing capacity could not be fully utilized for memory-intensive applications, which are limited by off-chip memory bandwidth and latency. Stencil computation has abundant parallelism and low computational intensity which make it a useful architectural evaluation benchmark. In this paper, we propose some memory optimizations for a stencil based application mgrid from SPEC 2 K benchmarks. Through exploiting data locality in 3-level memory hierarchies and tuning the thread granularity, we reduce the pressure on the off-chip memory bandwidth. To hide the long off-chip memory access latency, we further prefetch data during computation through double-buffer. In order to fully exploit the CPU-GPU heterogeneous system, we redistribute the computation between these two computing resource. Through all these optimizations, we gain 24.2 x speedup compared to the simple mapping version, and get as high as 34.3 x speedup when compared with a CPU implementation.

关键词： Concurrent computing Application software Acceleration Yarn Delay distributed processing distributed computing Bandwidth parallel processing Prefetching

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SEMCS: A Precise Memory-Hierarchy Simulation Framework on parallel Full-System Simulator

SEMCS: A Precise Memory-Hierarchy Simulation Framework on Pa...

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WASE International Conference on Information Engineering, ICIE

作者： Junjie Wu Xiaohui Pan Guanghui Liu Xuejun Yang National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha Hunan China

The memory wall problem makes researches on memory hierarchy more and more important. And in these researches, software simulation plays a significant role. To model the real runtime environment, full system simulators have been widely used. However, researchers are often perplexed by the precise problem when they run a parallel program on a full system multi-core simulator, especially in multiple configurations. Because the influence arising from operating system and the relative execution speed of parallel threads often make the performance of target programs uncertain. To solve the precise problem, this paper proposes a single execution multi-configuration simulation framework (SEMCS). Then we design and implement a Simics module, called trans-multicast using the SEMCS framework. Finally, we test a benchmark from SPEComp2001 on a four core processor in three memory hierarchy configurations. And the result has verified the effectiveness of the SEMCS framework.

关键词： Computational modeling Operating systems Testing Read-write memory computer simulation Concurrent computing Yarn Cache memory Laboratories distributed processing

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Laser-driven inertial ion focusing

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Physical Review E 2009年第1期79卷 015401(R)-015401(R)页

作者： H. B. Zhuo Wei Yu M. Y. Yu H. Xu X. Wang B. F. Shen Z. M. Sheng J. Zhang National Laboratory for Parallel and Distributed Processing School of Computer Science National University of Defense Technology Changsha 410073 China Shanghai Institute of Optics and Fine Mechanics Chinese Academy of Sciences Shanghai 201800 China Institute for Fusion Theory and Simulation Zhejiang University Hangzhou 310027 China Institute for Theoretical Physics I Ruhr University Bochum D-44780 Germany Department of Physics Jiaotong University Shanghai 200240 China

A Hohlraum-like configuration is proposed for realizing a simple compact source for neutrons. A laser pulse enters a tiny thin-shelled hollow-sphere target through a small opening and is self-consistently trapped in the cavity. The electrons in the inner shell-wall region are expelled by the light pressure. The resulting space-charge field compresses the local ions into a thin layer that becomes strongly heated. An inward expansion of ions into the shell cavity then occurs, resulting in the formation at the cavity center of a hot spot of ions at high density and temperature, similar to that in inertial electrostatic confinement.

关键词： laser fusion neutron sources particle beam focusing ELECTROSTATIC CONFINEMENT FUSION DEVICE

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