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High Performance Interconnect Network for Tianhe System

Journal of computer science & technology 2015年第2期30卷 259-272页

作者：廖湘科庞征王克非卢宇彤谢旻夏军董德尊所光 College of Computer National University of Defense Technology Changsha 410073 Science and Technology on Parallel and Distributed Processing Laboratory National Changsha 410073 China China University of Defense Technology State Key Laboratory of High Performance Computing National University of Defense Technology Changsha 410073 China

In this paper, we present the Tianhe-2 interconnect network and message passing services. We describe the architecture of the router and network interface chips, and highlight a set of hardware and software features effectively supporting high performance communications, ranging over remote direct memory access, collective optimization, hardwareenable reliable end-to-end communication, user-level message passing services, etc. Measured hardware performance results are also presented.

关键词： Tianhe-2 supercomputer interconnect network router architecture network interface architecture user-level message passing

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Workload-awared HPC system scalability analysis based on electronic technology developing

Workload-awared HPC system scalability analysis based on ele...

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2012 International Conference on Mechanical and Electronic Engineering, ICMEE 2012

作者： Lin, Yufei Tang, Yuhua Zhang, Xin National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9783642315152

As the electronic technology develops, the integration levels of CPUs and memories keep growing, and the speeds of communication devices are improved. The high-performance computing (HPC) systems consist of processing nodes and communication network, and their sizes are advanced by the development of electronic technology. Then the scalability of a large-scale parallel computing system, i.e. whether the computing performance is increased with the system size, becomes a major goal pursued by designers of parallel algorithms and high-performance parallel machines. parallel speedup is a popular way to measure the scalability. This paper proposes the definition of HPC system scalability based on speedup first, and then analyzes the influence of function G(P), which describes how the workload changes with processor number, on the system scalability. Through case studies, we analyze some typical programs based on our scalability theorems and the results show that our analysis approach is correct. © 2012 Springer-Verlag Berlin Heidelberg.

关键词： Scalability

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HyperSpring: Accurate and stable latency estimation in the hyperbolic space

HyperSpring: Accurate and stable latency estimation in the h...

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15th International Conference on parallel and distributed Systems, ICPADS '09

作者： Fu, Yongquan Wang, Yijie National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology China

ISBN: (纸本)9780769539003

Predicting network latencies between Internet hosts can efficiently support large-scale Internet applications, e.g., file sharing service and the overlay construction. Several study use the Hyperbolic space to model the Internet densecore and many-tendril structure. However, existing Hyperbolic space based embedding approaches are not designed for accurate latency estimation in the distributed context. We present HyperSpring, which estimates latency by modelling a mass spring system in the Hyperbolic similar with Vivaldi. HyperSpring adopts coordinate initialization to speed up the convergence of coordinate computation, uses multiple-round symmetric updates to escape from bad local minima, and stabilizes coordinates by compensating RTT measurements to reduce the coordinate drifts. Evaluation results based on a network trace of 226 PlanetLab nodes indicate that, compared to Euclidean-space based Vivaldi, HyperSpring provides performance improvements for most nodes, and incurs slightly higher distortions for a small number of nodes. © 2009 IEEE.

关键词： Hyperbolic space Latency estimation Mass spring field

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Automated WCET analysis based on program modes

Automated WCET analysis based on program modes

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1st International Workshop on Automation of Software Test, AST'06, Co-located with the 28th International Conference on Software Engineering, ICSE 2009

作者： Ji, Meng-Luo Wang, Ji Li, Shuhao Qi, Zhi-Chang School of Computer National University of Defense Technology China National Laboratory for Parallel and Distributed Processing China

ISBN: (纸本)1595934081

Program mode is a regular trajectory of the execution of a program that is determined by the values of its input variables. By exploiting program modes we may make Worst Case Execution Time (WCET) analysis more precise. This paper presents a novel method to automatically find program modes and calculate the WCET of programs. It consists of two phases. In phase one, we firstly automatically find the modes of a program by mode-relevant program slicing;then we compute the precondition for each mode using a path-wise test data generation method;after that, we can either conclude that it is an infeasible path, or get its precondition. In phase two, we calculate the WCET estimate of each given mode for modern RISC processors with caches and pipelines. The experiments are demonstrated to show the effectiveness of the method. Copyright 2006 ACM.

关键词： Real time systems

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Automating software FMEA via formal analysis of dependence relations

Automating software FMEA via formal analysis of dependence r...

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32nd Annual IEEE International computer Software and Applications Conference, COMPSAC 2008

作者： Dong, Wei Wang, Ji Zhao, Changzhi Zhang, Xian Tian, Jie School of Computer National University of Defense Technology China National Laboratory for Parallel and Distributed Processing China

ISBN: (纸本)9780769532622

The paper presents the ongoing work of studying FMEA method for embedded safety critical software via formal analysis of various dependence relations among software elements, which can fairly improve the automation and precision of both system level and detailed level FMEA. These dependence relations are depicted by the formal models abstracted from software design and implementation, and the FMEA processes for both structural and object-oriented software are proposed respectively. The initial result of case study shows the effectiveness of the approach. I 2008 IEEE.

关键词： Safety engineering

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UCBench: A user-centric benchmark suite for C code static analyzers

UCBench: A user-centric benchmark suite for C code static an...

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2012 IEEE International Conference on Information science and technology, ICIST 2012

作者： Liu, Jiangchao Chen, Liqian Dong, Longming Wang, Ji National Laboratory for Parallel and Distributed Processing School of Computer National University of Defence Technology Changsha China

ISBN: (纸本)9781457703454

In recent years, many C code static analyzers, with different abilities of bug detection, have appeared and been applied in various domains. There are so many choices that it becomes hard for programmers to know in detail the strengths as well as limitations of all these analyzers and to find the most suitable ones for their code. In this paper, we propose a benchmark for C code static analyzers, named UCBench, to provide quantitative and qualitative measurements for evaluating analyzers. Being different from other benchmarks, UCBench concentrates more on users' requirements rather than the improvements of bug detecting technique itself. The major components of UCBench include test case database, evaluation metrics and harness. We classify test cases into several groups according to their attributes and design various user-centric evaluation metrics. Besides, we develop some harness to automate the evaluation process. Finally, we demonstrate our benchmark suite over four C code static analyzers: Flawfinder, Cppcheck, Uno and Splint. © 2012 IEEE.

关键词： C (programming language)

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A case study of SWIM: Optimization of memory intensive application on GPGPU

A case study of SWIM: Optimization of memory intensive appli...

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International Symposium on parallel Architectures, Algorithms, and Programming

作者： Yi, Wei Tang, Yuhua Wang, Guibin Fang, Xudong National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology Changsha China

ISBN: (纸本)9780769543123

Recently, GPGPU has been adopted well in the High Performance Computing (HPC) field. The limited global memory bandwidth poses a great challenge to many GPGPU programmers trying to exploit parallelism within the CPUGPU heterogeneous platform. In this paper, we choose SWIM, a typical memory intensive application from the SPEC OMP 2001 benchmark suite, for case study. We attempt to optimize the performance and energy consumption of the application utilizing different memory access mechanisms and present optimization methods including matrix transposition and kernel fusion. The experimental results on the Intel CoreTM i920 CPU plus GeForce GTX 295 platform shows that, the proposed optimizing methods achieve a speedup of 8.7X over the original OpenMP program and reduce the energy consumption by 83% for the problem size of 2048*2048. © 2010 IEEE.

关键词： Energy utilization

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Impact of imprecise programming of memristor on building hardware neural network

Impact of imprecise programming of memristor on building har...

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2nd Annual Conference on Electrical and Control Engineering, ICECE 2011

作者： Zhu, Xuan National Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology ChangSha China

ISBN: (纸本)9781424481637

The application of memristor in building hardware neural network has accepted widespread interests, and may bring novel opportunities to neural computing. However, due to the limitation of programming precision, the conductance of memristor which represents stored information may deviate from theoretical value, and thus bring error to the neural computing results. In this paper, we analyze the impact of imprecise programming on building hardeware neural network through Monte Carlo simulation on feedback layer model. The results show that the fault-tolerance ability of neural network could well adapt to these errors, which further proves the potential of building neural networks using memristors. © 2011 IEEE.

关键词： Errors

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iRank: Supporting proximity ranking for peer-to-peer applications

iRank: Supporting proximity ranking for peer-to-peer applica...

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15th International Conference on parallel and distributed Systems, ICPADS '09

作者： Fu, Yongquan Wang, Yijie National Key Laboratory for Parallel and Distributed Processing School of Computer National University of Defense Technology China

ISBN: (纸本)9780769539003

Proximity ranking according to end-to-end network distances (e.g., Round-Trip Time, RTT) can reveal detailed proximity information, which is important in network management and performance diagnosis in distributed systems. However, to the best of our knowledge, there has been no similar work on this subject in the P2P computing field. We present a distributed rating method iRank, that enables proximity rankings by providing discrete ratings in a distributed manner. It formulates the proximity ranking as a rating problem that faithfully captures the proximity based on noisy distance measurements scalably and practically. The primary challenge in inferring proximity rankings is enforcing distributed ratings with complex rating policies. Our solution is based on reconstructing ratings by decomposing a centralized rating method Maximum Margin Matrix Factorization (MMMF) into independent sub-problems, that can be efficiently solved in a decentralized manner. By relaxing the dependence on infrastructure nodes that are a single point of failure and limit scalability, iRank can gracefully handle network churns. Through real network latency data sets, we demonstrate that iRank can predict ratings with low distortion, which are smaller than 20 percentage worse than the centralized method, in the context of synthetic complex rating policies. © 2009 IEEE.

关键词： Complex networks

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Improving performance portability for GPU-specific Open CL kernels on multi-core/many-core CPUs by analysis-based transformations

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Frontiers of Information technology & Electronic Engineering 2015年第11期16卷 899-916页

作者： Mei WEN Da-fei HUANG Chang-qing XUN Dong CHEN School of Computer National University of Defense Technology National Key Laboratory of Parallel and Distributed Processing

OpenCL is an open heterogeneous programming framework. Although OpenCL programs are func- tionally portable, they do not provide performance portability, so code transformation often plays an irreplaceable role. When adapting GPU-specific OpenCL kernels to run on multi-core/many-core CPUs, coarsening the thread granularity is necessary and thus has been extensively used. However, locality concerns exposed in GPU-specific OpenCL code are usually inherited without analysis, which may give side-effects on the CPU performance. Typi- cally, the use of OpenCL＇s local memory on multi-core/many-core CPUs may lead to an opposite performance effect, because local-memory arrays no longer match well with the hardware and the associated synchronizations are costly. To solve this dilemma, we actively analyze the memory access patterns using array-access descriptors derived from GPU-specific kernels, which can thus be adapted for CPUs by （1） removing all the unwanted local-memory arrays together with the obsolete barrier statements and （2） optimizing the coalesced kernel code with vectorization and locality re-exploitation. Moreover, we have developed an automated tool chain that makes this transformation of GPU-specific OpenCL kernels into a CPU-friendly form, which is accompanied with a scheduler that forms a new OpenCL runtime. Experiments show that the automated transformation can improve OpenCL kernel performance on a multi-core CPU by an average factor of 3.24. Satisfactory performance improvements axe also achieved on Intel＇s many-integrated-core coprocessor. The resultant performance on both architectures is better than or comparable with the corresponding OpenMP performance.

关键词： OpenCL Performance portability Multi-core/many-core CPU Analysis-based transformation

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