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Performance Evaluation of Different Data Value Prediction Schemes

Journal of Computer Science & Technology 2005年第5期20卷 615-623页

作者： Yong Xiao Xing-Ming Zhou National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410073 P.R. China

Data value prediction has been widely accepted as an effective mechanism to break data hazards for high performance processor design. Several works have reported promising performance potential. However, there is hardly enough information that is presented in a clear way about performance comparison of these prediction mechanisms. This paper investigates the performance impact of four previously proposed value predictors, namely last value predictor, stride value predictor, two-level value predictor and hybrid （stride-t-two-level） predictor. The impact of misprediction penalty, which has been frequently ignored, is discussed in detail. Several other implementation issues, including instruction window size, issue width and branch predictor are also addressed and simulated. Simulation results indicate that data value predictors act differently under different configurations. In some cases, simpler schemes may be more beneficial than complicated ones. In some particular cases, value prediction may have negative impact on performance.

关键词： data value predictors performance impact simulation

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PS-SIM: An Execution-Driven Performance Simulation Technology Based on Process-Switch

PS-SIM: An Execution-Driven Performance Simulation Technolog...

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International Conference on Advances in Computer Science, Environment, Ecoinformatics, and Education

作者： Guo, Xiaowei Lin, Yufei Xu, Xinhai Zhang, Xin National Laboratory for Parallel and Distributed Processing National University of Defense Technology China

ISBN: (纸本)9783642233234

Nowadays, the performance of large-scale parallel computer system improves continuously, and the system scale becomes extremely large. Performance prediction has become an important approach to guide system design, implementation and optimization. Simulation method is the most widely used performance prediction technology for large-scale parallel computer system. In this paper, after analyzing the extant problems, we proposed a novel execution-driven performance simulation technology based on process-switch. We designed a simulation framework named PS-SIM, and implemented a prototype system based on MPICH2. Finally, we verified the proposed approach by experiments. Experimental results show that the approach has high accuracy and simulation performance.

关键词： Performance Prediction Large-Scale parallel Computer System Execution-Driven Simulation MPICH

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A hyper-cube based P2P information service for data grid

A hyper-cube based P2P information service for data grid

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5th International Conference on Grid and Cooperative Computing, GCC 2006

作者： Ren, Hao Wang, Zhiying Liu, Zhong National Laboratory for Parallel and Distributed Processing NUDT China

ISBN: (纸本)0769526942

There are many researches use peer-to-peer model to organize the Grid Information Service (GIS) and have been testified which be able to improve scalability and reliability of Grid environment. However, Data Grid Information Service (DGIS) has its special requirements and all approaches of PIP model used in GIS cannot be applied to DGIS. In this paper, we propose a new approach for DGIS that imposes a deterministic P2P shape based on hypercube topology, which allows for very efficient query broadcasting. Furthermore, we proposed a transposition algorithm to optimize the overlay network's topology according to the access statistics between peers, making the peers always access each other become neighbor by transposing peer's place. The simulation shows that the transposition algorithm could significant improve searches efficiency. © 2006 IEEE.

关键词： Information services

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Towards a framework for scalable model checking of concurrent C programs

Towards a framework for scalable model checking of concurren...

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2nd International Symposium on Leveraging Applications of Formal Methods, Verification and Validation, ISoLA 2006

作者： Ji, Wang Yi, Xiaodong Yang, Xuejun National Laboratory for Parallel and Distributed Processing Changsha China

ISBN: (纸本)0769530710

The paper presents a novel framework for scalable model checking of concurrent C programs. With the idea of verification reuse, it shows an integrated approach to efficient reduction of state space by abstraction, symbolic representation and dynamic partial-order reduction (DPOR) techniques. The framework is founded on an over-approximated model of the concurrent program by variable abstraction, and combines DPOR with lightweight symbolic execution to generate the symbolic conditions for all locations, called α-conditions, which are intended for verification reuse. The α-conditions of a location are weak approximation of the conditions that must be satisfied at that location so as to guarantee the temporal safety properties to be verified. These conditions will be checked for reusing the previous exploration in verification, and will be iteratively refined under the guidance of spurious counterexamples. The presented framework is demonstrated by several experiments including a concurrent software system whose server and client processes are derived from openssl-0.9.6c C source codes implementing the SSL protocol. © 2007 IEEE.

关键词： Model checking

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Simulation study of N-hit SET variation in differential cascade voltage switch logical circuits

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Science China(Information Sciences) 2015年第2期58卷 165-173页

作者： HUANG PengCheng CHEN ShuMing CHEN JianJun WU ZhenYu LIANG ZhengFa HU ChunMei LIANG Bin LIU BiWei Micro-electronics and Microprocessor Institute College of Computer ScienceNational University of Defense Technology National Laboratory for Parallel and Distributed Processing College of Computer ScienceNational University of Defense Technology

The advancement in the process leads to more concern about the Single Event(SE) sensitivity of the Differential Cascade Voltage Switch Logic(DCVSL) circuits. The simulation results indicate that the Single Event Transient(SET) generated at the DCVSL gate is much larger than that at the ordinary CMOS gate, and their SET variation is different. Based on charge collection, in this paper, the effective collection time theory is proposed to set forth the SET pulse generated at the DCVSL gate. Through 3D TCAD mixed-mode simulation in 65 nm twin-well bulk CMOS process, the effects on SET variation of device parameters such as well contact size and environment parameters such as voltage are investigated.

关键词： differential cascade voltage switch logic(DCVSL) single event transient(SET) effective collection time pulse feedback feature(PFF) across-coupled structure

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Static Power Optimization for Homogeneous Multiple GPUs Based on Task Partition

Static Power Optimization for Homogeneous Multiple GPUs Base...

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2nd International Congress on Computer Applications and Computational Science (CACS 2011)

作者： Lin, Yisong Tang, Tao Wang, Guibin National Laboratory of Parallel and Distributed Processing National University of Defense Technology Changsha China

ISBN: (纸本)9783642283079;9783642283086

Recently, GPU has been widely used in High Performance Computing (HPC). In order to improve computational performance, several GPUs are integrated into one computer node in practical system. However, power consumption of GPUs is very high and becomes as bottleneck to its further development. In doing so, optimizing power consumption have been draw broad attention in the research area and industry community. In this paper, we present an energy optimization model considering performance constraint for homogeneous multi-GPUs, and propose a performance prediction model when task partitioning policy is specified. Experiment results validate that the model can accurately predict the execution of program for single or multiple GPUs, and thus reduce static power consumption by the guide of task partition.

关键词： Electric power utilization

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Mirror image:newfangled cell-level layout technique for single-event transient mitigation

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Chinese Science Bulletin 2014年第23期59卷 2850-2858页

作者： Pengcheng Huang Shuming Chen Zhengfa Liang Jianjun Chen Chunmei Hu Yibai He Micro-electronics and Microprocessor Institute National University of Defense Technology National Laboratory for Parallel and Distributed Processing National University of Defense Technology

Recent years,the hardening of combinational circuits is becoming a common *** the transistor-level hardening technique,the cell-level hardening technique,a divide and conquer strategy,can substantially make use of some typical character in the cell-circuit module to mitigate single event transient(SET)*** mirror image(MI)technique proposed in this paper can adequately enhance the charge sharing in those cell-circuits with stage-by-stage inverter-like structure.3D TCAD mixed-mode simulation have been performed in 65 nm twinwell bulk CMOS process,the results indicate that the MI technique can almost reduce the SET pulse width from the anterior-stage PMOS over 25%,and can mitigate the SET pulse width from the posterior-stage PMOS about 10%.The MI technique,a represent of the cell-level technique,may be the future of the hardening of combinational circuits.

关键词：单事件技术细胞瞬态镜像组合逻辑电路次布 CMOS工艺

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Implementation of ternary Shor's algorithm based on vibrational states of an ion in anharmonic potential

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Chinese Physics B 2015年第3期24卷 157-165页

作者：刘威陈书明张见吴春旺吴伟陈平形 College of Computer National University of Defense Technology Science and Technology on Parallel and Distributed Processing Laboratory (PDL) National University of Defense Technology College of Science National University of Defense Technology

It is widely believed that Shor＇s factoring algorithm provides a driving force to boost the quantum computing ***, a serious obstacle to its binary implementation is the large number of quantum gates. Non-binary quantum computing is an efficient way to reduce the required number of elemental gates. Here, we propose optimization schemes for Shor＇s algorithm implementation and take a ternary version for factorizing 21 as an example. The optimized factorization is achieved by a two-qutrit quantum circuit, which consists of only two single qutrit gates and one ternary controlled-NOT gate. This two-qutrit quantum circuit is then encoded into the nine lower vibrational states of an ion trapped in a weakly anharmonic potential. Optimal control theory（OCT） is employed to derive the manipulation electric field for transferring the encoded states. The ternary Shor＇s algorithm can be implemented in one single step. Numerical simulation results show that the accuracy of the state transformations is about 0.9919.

关键词： ternary Shor＇s algorithm anharmonic ion trapping optimal control theory vibrational state

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Optimizing guest swapping using elastic and transparent memory provisioning on virtualization platform

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Frontiers of Computer Science 2016年第5期10卷 908-924页

作者： Xi LI Pengfei ZHANG Rui CHU Huaimin WANG School of Information Science and Engineering Central South University Changsha 410083 China National Laboratory for Parallel and Distributed Processing National University of Defense Technology Changsha 410008 China

On virtualization platforms, peak memory de- mand caused by hotspot applications often triggers page swapping in guest OS, causing performance degradation in- side and outside of this virtual machine （VM）. Even though host holds sufficient memory pages, guest OS is unable to utilize free pages in host directly due to the semantic gap between virtual machine monitor （MM） and guest operat- ing system （OS）. Our work aims at utilizing the free memory scattered in multiple hosts in a virtualization environment to improve the performance of guest swapping in a transparent and implicit way. Based on the insightful analysis of behav- ioral characteristics of guest swapping, we design and im- plement a distributed and scalable framework HybridSwap. It dynamically constructs virtual swap pools using various policies, and builds up a synthetic swapping mechanism in a peer-to-peer way, which can adaptively choose different vir- tual swap pools. We implement the prototype of HybridSwap and evaluate it with some benchmarks in different scenar- ios. The evaluation results demonstrate that our solution has the ability to promote the guest swapping efficiency indeed and shows a double performance promotion in some cases. Even in the worst case, the system overhead brought by Hy- bridSwap is acceptable.

关键词： virtualization memory management guestswapping performance degradation

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Mobility of internet-based virtual computing environment

Mobility of internet-based virtual computing environment

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15th International Conference on parallel and distributed Systems, ICPADS '09

作者： Shen, Siqi Wang, Ji Shen, Rui Zhang, Shengdong Fan, Pei National Laboratory for Parallel and Distributed Processing Changsha 410073 China

ISBN: (纸本)9780769539003

The Internet-based Virtual Computing Environment (iVCE) provides on-demand aggregation and autonomic collaboration mechanisms to facilitate the utilization of autonomous and dynamic Internet resources. Load balancing and fault tolerance are important issues when scheduling those transient resources. In this paper, we propose a mobility mechanism for the migration of various roles of agents in the iVCE platform. The mobility mechanism involves two parts of the iVCE platform: role container layer and event service layer. At the role container layer, a novel approach is proposed to handle the code and data mobility issue. At the event service layer, an efficient routing reconfiguration protocol is proposed based on a publish/subscribe system over DHTs to facilitate task migrations. Certain conditions must be satisfied before the migration of an agent to ensure the correctness of the whole process. Experiments are conducted to evaluate the performance of the mobility mechanism, and the experimental results show that it is suitable for implementing load balancing and fault tolerance in the iVCE. © 2009 IEEE.

关键词： Fault tolerance

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