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Workshops on Object-Oriented Technology, ECOOP 1997

作者： Ahlander, Krister Ahtee, Tero Holst, Wade Hung, Kitty Karadurak, Selma Kehr, Roger Nowack, Palle Tai, Stefan Department of Scientific Computing Box 120 Uppsala Sweden Tampere University of Technology Software Systems Laboratory Finland Department of Computer Science University of Alberta Canada South Bank University United Kingdom London Guildhall University CISM Dept. 100 Minories Tower Hill London United Kingdom Department of Computer Science WG Distributed Systems Technical University of Darmstadt Germany Department of Computer Science Aalborg University Fredrik Bajers Vej 7E Aalborg Ø Denmark Technical University Berlin Sekr. E-N 7 Einsteinufer 17 Berlin Germany

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parallel algorithms for simultaneous scheduling, binding and floorplanning in high-level synthesis

Parallel algorithms for simultaneous scheduling, binding and...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： P. Prabhakaran P. Banerjee Center for Reliable and High-Performance Computing Coordinated Science Laboratory University of Illinois Urbana-Champaign IL USA Center for Parallel and Distributed Computing Department of Electrical and Computer Engineering Northwestern University Evanston IL USA

With small device features in submicron technologies, interconnection delays play a dominant part in cycle time. Hence, it is important to consider the impact of physical design during high level synthesis. In comparison to a traditional approach which separates high-level synthesis from physical design, an algorithm which is able to make these stages interact very closely, would result in solutions with lower latency and area. However, such an approach could result in increased runtimes. parallel processing is an attractive way of reducing the runtimes. In this paper, two parallel algorithms for simultaneous scheduling, binding and floorplanning algorithm are presented. A detailed hardware model is considered, taking into account multiplexor and register areas and delays. Experimental results are reported on an IBM SP-2 multicomputer, with close to linear speedups for a set of benchmark circuits.

关键词： parallel algorithms High level synthesis Runtime Integrated circuit interconnections Delay effects Algorithm design and analysis parallel processing Scheduling algorithm Hardware Registers

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Performance measurement using low perturbation and high precision hardware assists

Performance measurement using low perturbation and high prec...

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Real-Time systems Symposium (RTSS)

作者： A. Mink W. Salamon J.K. Hollingsworth R. Arunachalam Scalable Parallel Systems Group Information Technology Laboratory National Institute for Standards and Technology Gaithersburg MD USA Computer Science Department University of Maryland College Park MD USA

We present the design and implementation of MultiKron PCI, a hardware performance monitor that can be plugged into any computer with a free PCI bus slot. The monitor provides a series of high-resolution timers, and the ability to monitor the utilization of the PCI bus. We also demonstrate how the monitor can be integrated with online performance monitoring tools such as the Paradyn parallel performance measurement tools to improve the overhead of key timer operations by a factor of 25. In addition, we present a series of case studies using the MultiKron hardware performance monitor to measure and tune high-performance parallel completing applications. By using the monitor, we were able to find and correct a performance bug in a popular implementation of the MPI message passing library that caused some communication primitives to run at one half their potential speed.

关键词： Measurement Hardware computerized monitoring Performance evaluation NIST Debugging Timing Runtime Counting circuits Clocks

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A mathematical model, heuristic, and simulation study for a basic data staging problem in a heterogeneous networking environment

A mathematical model, heuristic, and simulation study for a ...

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Heterogeneous Computing Workshop

作者： Min Tan M.D. Theys H.J. Siegel N.B. Beck M. Jurczyk Cisco Systems Inc. San Jose CA USA Parallel Processing Laboratory School of Electrical and Computer Engineering Purdue University West Lafayette IN USA Department of Computer Engineering and Computer Science University of Missouri Columbia Columbia MO USA

Data staging is an important data management problem for a distributed heterogeneous networking environment, where each data storage location and intermediate node may have specific data available, storage limitations, and communication links. Sites in the network request data items and each item is associated with a specific deadline and priority. It is assumed that not all requests can be satisfied by their deadline. The work concentrates on solving a basic version of the data staging problem in which all parameter values for the communication system and the data request information represent the best known information collected so far and stay fixed throughout the scheduling process. A mathematical model for the basic data staging problem is introduced. Then, a multiple-source shortest-path algorithm based heuristic for finding a suboptimal schedule of the communication steps for data staging is presented. A simulation study is provided, which evaluates the performance of the proposed heuristic. The results show the advantages of the proposed heuristic over two random based scheduling techniques. This research, based on the simplified static model, serves as a necessary step toward solving the more realistic and complicated version of the data staging problem involving dynamic scheduling, fault tolerance, and determining where to stage data.

关键词： Mathematical model computer networks distributed computing Data engineering Military computing Intelligent networks computer network management Environmental management Memory Satellite broadcasting

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Generic systolic array for genetic algorithms

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IEE PROCEEDINGS-computerS AND DIGITAL TECHNIQUES 1997年第2期144卷 107-119页

作者： Megson, GM Bland, IM Department of Computer Science Algorithm Engineering Research Group Parallel Emergent and Distributed Architectures Laboratory (PEDAL) University of Reading Reading United Kingdom

The authors present a systolic design for a simple GA mechanism which provides high throughput and unidirectional pipelining by exploiting the inherent parallelism in the genetic operators. The design computes in O(N + G) time steps using O(N-2) cells where N is the population size and G is the chromosome length. The area of the device is independent of the chromosome length and so can be easily scaled by replicating the arrays or by employing fine-grain migration. The array is generic in the sense that it does not rely on the fitness function and can be used as an accelerator for any GA application using uniform crossover between pairs of chromosomes. The design can also be used in hybrid systems as an complement existing designs and fitness function acceleration and island-style population management.

关键词： field programmable gate array optimisation algorithm systolic array

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Using the causal domain to specify and verify distributed programs

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ACTA INFORMATICA 1997年第9期34卷 667-686页

作者： Garg, VK Tomlinson, AI Parallel and Distributed Systems Laboratory Department of Electrical and Computer Engineering The University of Texas at Austin Austin TX 78712 USA (http://maple.ece.utexas.edu) US

A system for specification and proof of distributed programs is presented. The method is based directly on the partial order of local states (poset) and avoids the notions of time and simultaneity. Programs are specified by documenting the relationship between local states which are adjacent to each other in the poset. Program properties are defined by stating properties of the poset. Many program properties can be expressed succinctly and elegantly using this method because poset properties inherently account for varying processor execution speeds. The system utilizes a proof technique which uses induction on the complement of the causally precedes relation and is shown to be useful in proving poset properties. We demonstrate the system on three example algorithms: vector clocks, mutual exclusion, and direct dependency clocks.

关键词： parallel algorithms

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An efficient local address generation for the block-cyclic distribution 3

An efficient local address generation for the block-cyclic d...

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3rd International Conference on Algorithms and Architectures for parallel Processing, ICA3PP 1997

作者： Kwon, Oh-Young Kim, Tae-Geun Han, Tack-Don Yang, Sung-Bong Kim, Shin-Dug Distributed Computing Lab. Systems Engineering Research Institute 1 Ueun-dong Yusong-gu Taejon305-333 Korea Republic of Parallel Processing System Laboratory Dept. of Computer Science Yonsei University Seoul120-749 Korea Republic of

ISBN: (纸本)0780342291

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time ΔM table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a ΔM table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time ΔM table generation method is faster than other algorithms in ΔM table generation time and access time for 10,000 array elements. © 1997 IEEE.

关键词： Virtual addresses

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An efficient local address generation for the block-cyclic distribution

An efficient local address generation for the block-cyclic d...

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IEEE International Conference on Algorithms and Architectures for parallel Processing (ICAP)

作者： Oh-Young Kwon Tae-Geun Kim Tack-Don Han Sung-Bong Yang Shin-Dug Kim Distributed Computing Laboratory Systems Engineering Research Institute Taejon South Korea Parallel Processing System Laboratory Department of Computer Science Yonsei University Seoul South Korea

ISBN: (纸本)0780342291

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time /spl Delta/M table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a /spl Delta/M table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time /spl Delta/M table generation method is faster than other algorithms in /spl Delta/M table generation time and access time for 10,000 array elements.

关键词： Runtime Equations distributed computing systems engineering and theory parallel processing Laboratories computer science parallel languages Upper bound Automata

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A data placement strategy on MZR for VOD servers

A data placement strategy on MZR for VOD servers

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International Conference on parallel and distributed systems (ICPADS)

作者： Jeong-Won Kim Hyoung-Roung Lim Young-Ju Kim Ki-Dong Chung Parallel Multimedia Laboratory Department of Computer Science Pusan National University South Korea Systems Engineering Research Institute Taejon South Korea

ISBN: (纸本)0818682272

The number of concurrent users in VOD servers mainly depend on the disk placement strategies of video blocks. Especially, the storage server should make the most of MZR (multi-zone recording) disks' characteristics. The variable transfer rates and capacity in zones feature the MZR disk, so the outward zones have more transfer rates and capacity than inward zones. Also, Users' access patterns concentrate on the popular videos. So, if the popular video blocks are placed at the outward zones, the number of concurrent users can be increased. In this paper we present the popularity-based variable way placement strategy for disk groups (PVW) based on the LP and the SHP. The PVW aims to effectively support popular streams of high access rates without additional storage capacity. The more popular video blocks are to be placed in all disk groups to utilize the total bandwidth of a storage subsystem, and the less popular video blocks are to be placed in the small disk groups. By the simulation study, we have found that more users could be supported by this strategy.

关键词： Bandwidth Space technology Video on demand Videoconference Hard disks Disk recording Video recording computer science systems engineering and theory Tiles

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Scalable hardware priority queue architectures for high-speed packet switches

Scalable hardware priority queue architectures for high-spee...

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Real-Time Technology and Applications Symposium

作者： S.-W. Moon K.G. Shin J. Rexford Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA Network Mathematics Research Networking and Distributed Systems AT and T Research Laboratories Murray Hill NJ USA

In packet-switched networks, queueing of packets at the switches can result when multiple connections share the same physical link. To accommodate a large number of connections, a switch can employ link-scheduling algorithms to prioritize the transmission of the queued packets. Due to the high-speed links and small packet sizes, a hardware solution is needed for the priority queue in order to make the link schedulers effective. But for good performance, the switch should also support a large number of priority levels (P) and be able to buffer a large number of packets (N). So a hardware priority queue design must be both fast and scalable (with respect to N and P) in order to be implemented effectively. In this paper we first compare four existing hardware priority queue architectures, and identify scalability limitations on implementing these existing architectures for large N and P. Based on our findings, we propose two new priority queue architectures, and evaluate them using simulation results from Verilog HDL and Epoch implementations.

关键词： Packet switching Switches Traffic control Scheduling algorithm Asynchronous transfer mode Hardware design languages Communication system traffic control computer architecture Moon Real time systems

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