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An efficient local address generation for the block-cyclic distribution 3

An efficient local address generation for the block-cyclic d...

引用

3rd International Conference on Algorithms and Architectures for parallel Processing, ICA3PP 1997

作者： Kwon, Oh-Young Kim, Tae-Geun Han, Tack-Don Yang, Sung-Bong Kim, Shin-Dug Distributed Computing Lab. Systems Engineering Research Institute 1 Ueun-dong Yusong-gu Taejon305-333 Korea Republic of Parallel Processing System Laboratory Dept. of Computer Science Yonsei University Seoul120-749 Korea Republic of

ISBN: (纸本)0780342291

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time ΔM table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a ΔM table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time ΔM table generation method is faster than other algorithms in ΔM table generation time and access time for 10,000 array elements. © 1997 IEEE.

关键词： Virtual addresses

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A multimedia information system for document authoring, indexing and presentation

A multimedia information system for document authoring, inde...

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IEEE Annual International computer Software and Applications Conference (COMPSAC)

作者： Z.K. Li Y.F. Day H. Fahmi A. Ghafoor School of Electrical and Computer Engineering Distributed Multimedia Systems Laboratory Purdue University West Lafayette IN USA

The authors present a multimedia management system that supports creation, storing, indexing and presentation of complex multimedia objects. An object-oriented data model is proposed to capture the content, spatial and temporal semantics of multimedia data. Based on this model, they design a query processor to perform multi-dimension search on multimedia data.

关键词： Multimedia systems Information systems Indexing Multimedia databases Object oriented modeling Data models Multimedia computing Videoconference Information retrieval Quality of service

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Scalable hardware priority queue architectures for high-speed packet switches

Scalable hardware priority queue architectures for high-spee...

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3rd IEEE Real-Time Technology and Applications Symposium

作者： Moon, SW Shin, KG Rexford, J Real-Time Computing Laboratory Dept. of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI 48109 United States Network Mathematics Research Networking and Distributed Systems ATandT Labs Research Murray Hill NJ 07974 United States

ISBN: (纸本)0818680164

In packet-switched networks, queueing of packets at the switches can result when multiple connections share the same physical link. To accommodate a large number of connections, a switch can employ link-scheduling algorithms to prioritize the transmission of the queued packets. Due to the high-speed links and small packet sizes, a hardware solution is needed for the priority queue in order to make the link schedulers effective. But for good performance, the switch should also support a large number of priority levels (P) and be able to buffer a large number of packets (N). So a hardware priority queue design must be both fast and scalable (with respect to N and P) in order to be implemented effectively. In this paper, we first compare four existing hardware priority queue architectures, and identify scalability limitations on implementing these existing architectures for large N and P. Based on our findings, we propose two new priority queue architectures, and evaluate them using simulation results from Verilog HDL and Epoch implementations.

关键词： computer architecture

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An efficient local address generation for the block-cyclic distribution

An efficient local address generation for the block-cyclic d...

引用

IEEE International Conference on Algorithms and Architectures for parallel Processing (ICAP)

作者： Oh-Young Kwon Tae-Geun Kim Tack-Don Han Sung-Bong Yang Shin-Dug Kim Distributed Computing Laboratory Systems Engineering Research Institute Taejon South Korea Parallel Processing System Laboratory Department of Computer Science Yonsei University Seoul South Korea

ISBN: (纸本)0780342291

In order to generate local addresses for an array section A(l:h:s) with block-cyclic distribution, an efficient compiling method is required. In this paper, two local address generation methods for the block-cyclic distribution are presented. One is a simple local address generation method that is modified from the virtual-block scheme. The other is a linear-time /spl Delta/M table construction method. The array elements of A(l:h:s) to be accessed at run-time build up a family of lines. By using the equation of the lines, a /spl Delta/M table can be generated in O(k) time. Experimental results show that a simple local address generation method has poor performance but a linear-time /spl Delta/M table generation method is faster than other algorithms in /spl Delta/M table generation time and access time for 10,000 array elements.

关键词： Runtime Equations distributed computing systems engineering and theory parallel processing Laboratories computer science parallel languages Upper bound Automata

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Real-time scheduling for synchronized presentation of multimedia information in distributed multimedia systems

Real-time scheduling for synchronized presentation of multim...

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Workshop on Object-Oriented Real-Time Dependable systems (WORDS)

作者： R. Paul M.F. Khan S. Baqai A. Ghafoor Testing and Evaluation Washington D.C. DC USA Distributed Multimedia Systems Laboratory School of Electrical & Computer Engineering Purdue University West Lafayette IN USA Distributed Multimedia Systems Laboratory Purdue University West Lafayette IN USA

distributed, networked multimedia information systems are expected to play a major role in the information age of today. Presentation of multimedia information requires temporal synchronization within and among different objects. Network heterogeneity, resource constraints, and random traffic characteristics necessitate intelligent mechanisms for synchronized presentation of multimedia data in distributed multimedia systems. The computational complexity of any such synchronization method has to be small for real-time presentation. The authors use intelligent scheduling procedures to guarantee intra-stream and inter-stream synchronization under network resource constraints. They use the notion of quality of presentation for multimedia data to evaluate the effectiveness of these scheduling algorithms for different resource instances. They present two low complexity (O(n log n), where n is the total number of multimedia presentation units to be scheduled) heuristic scheduling algorithms for real-time applications. They have implemented these algorithms on an asynchronous transfer mode (ATM) network testbed and discuss their performance with respect to two different quality parameters.

关键词： Multimedia systems Computational intelligence Intelligent networks Scheduling algorithm Asynchronous transfer mode Information systems Telecommunication traffic Computational complexity Processor scheduling Testing

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Ensuring quality of service for multimedia applications in a LAN environment

Ensuring quality of service for multimedia applications in a...

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IEEE International Symposim on High Assurance systems engineering

作者： H. Fahmi R.A. Paul A. Bashandy A. Ghafoor Distributed Multimedia Systems Laboratory School of Electrical and Computer Engineering Purdue University West Lafayette IN USA Testing and Evaluation Washington D.C. DC USA

We present a mechanism for dynamically allocating network resources in asynchronous LANs for supporting multimedia applications that require quality of service guarantee. The approach is based on the concept of time division multiple access (TDMA). It uses a centralized controller as the bandwidth manager. The total bandwidth is partitioned into two segments: one is used for serving multimedia connections and the other for the normal CSMA/CD sessions. Experimental results reveal that the performance of the proposed scheme is substantially better than that of the random access mechanism. In particular, transmission rates for multimedia hosts are improved significantly with low jitter variations in media streams.

关键词： Quality of service Local area networks Access protocols Time division multiple access Multiaccess communication Bandwidth Resource management Jitter Ethernet networks Asynchronous transfer mode

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Scalable hardware priority queue architectures for high-speed packet switches

Scalable hardware priority queue architectures for high-spee...

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Real-Time Technology and Applications Symposium

作者： S.-W. Moon K.G. Shin J. Rexford Real-Time Computing Laboratory Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA Network Mathematics Research Networking and Distributed Systems AT and T Research Laboratories Murray Hill NJ USA

In packet-switched networks, queueing of packets at the switches can result when multiple connections share the same physical link. To accommodate a large number of connections, a switch can employ link-scheduling algorithms to prioritize the transmission of the queued packets. Due to the high-speed links and small packet sizes, a hardware solution is needed for the priority queue in order to make the link schedulers effective. But for good performance, the switch should also support a large number of priority levels (P) and be able to buffer a large number of packets (N). So a hardware priority queue design must be both fast and scalable (with respect to N and P) in order to be implemented effectively. In this paper we first compare four existing hardware priority queue architectures, and identify scalability limitations on implementing these existing architectures for large N and P. Based on our findings, we propose two new priority queue architectures, and evaluate them using simulation results from Verilog HDL and Epoch implementations.

关键词： Packet switching Switches Traffic control Scheduling algorithm Asynchronous transfer mode Hardware design languages Communication system traffic control computer architecture Moon Real time systems

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Prefetching and caching for query scheduling in a special class of distributed applications 25

Prefetching and caching for query scheduling in a special cl...

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25th International Conference on parallel Processing, ICPP 1996

作者： Sinha, A. Chase, C. Parallel and Distributed Systems Laboratory Department of Electrical and Computer Engineering University of Texas AustinTX78712 United States

ISBN: (纸本)081867623X

We analyze the scheduling aspects of database queries submitted to an abstract model of a very large distributed system. The essential elements of this model are: (a) a finite number of identical processing nodes with limited storage capacity, (b) a finite number of queries to be serviced, (c) a very large read-only data set that is shared by all queries and (d) a fixed inter-node communication latency. This framework models an important class of applications that use distributed processing of very large data sets. Examples of these applications exist in the very large database and multimedia problem domains. To meet the objective of minimizing flow time of queries while exploiting inter-query locality, various heuristics are proposed and evaluated through extensive simulation. © 1996 IEEE.

关键词： Scheduling

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Prefetching and caching for query scheduling in a special class of distributed applications

Prefetching and caching for query scheduling in a special cl...

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International Conference on parallel Processing (ICPP)

作者： A. Sinha C. Chase Parallel and Distributed Systems Laboratory Electrical and Computer Engineering University of Texas Austin Austin TX USA

关键词： Prefetching Processor scheduling Application software Delay Multimedia databases Network servers Laboratories distributed databases distributed processing Computational modeling

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Design and evaluation of an environment APE for automatic parallelization of programs

Design and evaluation of an environment APE for automatic pa...

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International Symposium on parallel Architectures, Algorithms and Networks (ISPAN)

作者： V. Chaudhary Chengzhong Xu S. Roy Jialin Ju V. Sinha Laiwu Luo Parallel and Distributed Computing Laboratory Department of Electrical and Computer Engineering Wayne State University MI USA

In this paper, we present the design and evaluation of a compiler system, called APE, for automatic parallelization of scientific and engineering applications on distributed memory computers. APE is built on top of SUIF compiler. It extends SUIF with capabilities in parallelizing loops with non-uniform cross-iteration dependencies, and in handling loops that have indirect access patterns. We have evaluated the effectiveness of SUIF with several CFD test codes, and found that SUIF handles uniform loops over dense and regular data structures very well. For non-uniform loops, an innovative and efficient parallelization approach based on convex theory have been proposed and is being implemented. We have also presented a class of scalable algorithms for parallel distribution and redistribution of unstructured data structures during parallelizing irregular loops.

关键词： Program processors distributed computing Concurrent computing Computational fluid dynamics Data structures Quantum computing Programming profession parallel processing Design engineering Optimizing compilers

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