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IEEE Electron Device Letters 2025年第5期46卷 705-708页

作者： Chen, Yi-Ho Chu, Fu-Chuan Aslam, Muhammad Lee, Yao-Jen Li, Yiming Samukawa, Seiji Parallel and Scientific Computing Laboratory Graduate Degree Program of College of Electrical and Computer Engineering National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Solid State Devices Section Electronic System Research Division National Chung-Shan Institute of Science and Technology Taoyuan325 Taiwan Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science international graduate program National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Institute of Pioneer Semiconductor Innovation National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Parallel and Scientific Computing Laboratory Institute of Communications Engineering Institute of Biomedical Engineering Department of Electronics and Electrical Engineering Institute of Pioneer Semiconductor Innovation Institute of Artificial Intelligence Innovation National Yang Ming Chiao Tung University Hsinchu300093 Taiwan Institute of Communications Engineering Department of Electronics and Electrical Engineering National Yang Ming Chiao Tung University Hsinchu300093 Taiwan

Recess gate etching is a critical technique for achieving enhancement-mode (E-mode) AlGaN/GaN high-electron mobility transistors (HEMTs) because the interface is susceptible to the etching damage. This study fabricates recess gates using the neutral beam etching (NBE) technique. By adjusting the aperture thickness in the NBE apparatus, we simulate both NB-mode and plasma-mode etching. The electrical characteristics of E-mode HEMTs fabricated using these two modes are analyzed and compared through DC, noise, and pulsed IV measurements. The results demonstrate that NB-recessed HEMTs exhibit superior performance. © 2025 IEEE.

关键词： Aluminum gallium nitride

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A Physical-Based Artificial Neural Networks Compact Modeling Framework for Emerging FETs

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IEEE Transactions on Electron Devices 2024年第1期71卷 223-230页

作者： Yang, Ya-Shu Li, Yiming Kola, Sekhar Reddy Reddy National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory The Institute of Communications Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Institute of Communications Engineering Institute of Biomedical Engineering Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan

We report a compact modeling framework based on the Grove-Frohman (GF) model and artificial neural networks (ANNs) for emerging gate-all-around (GAA) MOSFETs. The framework consists of two ANNs;the first ANN constructed with the drain current model not only can capture the main trend of device I - V characteristics but also can predict its variation even when the amount of training data for the ANN is insufficient or outside the range of applied biases. The second one is then designed to improve the model accuracy by further minimizing the errors between the target and the model outputs. We implement the proposed framework to accurately model emerging GAA nanosheet (NS) MOSFETs and complementary FETs (CFETs) without suffering from divergent issues in circuit simulation. In addition, nonphysical behaviors, such as nonzero current at zero bias, do not occur in the modeling framework. Compared to recently reported machine-learning (ML) models, our approach can achieve a similar level of model accuracy with merely 20% amount of the training data. © 1963-2012 IEEE.

关键词： Neural networks

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ON MAXIMA OF DUAL FUNCTION OF THE CDT SUBPROBLEM

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Journal of Computational Mathematics 2001年第2期19卷 113-124页

作者： Xiong-da Chen Ya-xiang Yuan Reserach Development Center of Parallel Software Institute of SoftwareBeijing 100080China State Key Laboratory of Scientific and Engineering Computing Institute of Computational Mathematics and Ssientific/Engineering ComputingAcademy of Mathematics and Systems SciencesChinese Academy of SciencesBeijing 100080China

Focuses on a study which determined the geometry meaning of the maxima of the CDT mathematical subproblem's dual function. Properties of trust region subproblem; Approximation of the CDT feasible region; Relations... 详细信息

关键词： trust region subproblem global minimizer approximation

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Impact of geometry aspect ratio on 10-nm gate-all-around silicon-germanium nanowire field effect transistors 14

Impact of geometry aspect ratio on 10-nm gate-all-around sil...

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2014 14th IEEE International Conference on Nanotechnology, IEEE-NANO 2014

作者： Chao, Pei-Jung Li, Yiming Parallel and Scientific Computing Laboratory Institute of Biomedical Engineering National Chaio Tung University Hsinchu300 Taiwan

ISBN: (纸本)9781479956227

In this paper, we study electrical characteristics of gate-all-around (GAA) silicon-germanium (SiGe) nanowire field effect transistors (NWFETS) with different aspect ratio (AR) of channel. Device characteristics: the subthreshold swing (SS), the drain induced barrier lowering (DIBL), and the ION/IOFF ratio are simulated by using three-dimensional quantum mechanically corrected device simulation. Electrical characteristics of 10-nm-gate GAA Si1-xGex NWFET devices are explored with respect to different thickness of SiGe and Ge's mole fraction. It is investigated that an ellipse-shaped channel with a small aspect ratio possesses better DC characteristics, compared with the one which has large AR due to its good gate controllability. © 2014 IEEE.

关键词： Aspect ratio

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Optimization of physics-based equivalent circuits for microstrip patch antennas

Optimization of physics-based equivalent circuits for micros...

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2007 IEEE Antennas and Propagation Society International Symposium, AP-S

作者： Chiu, Tang-Jung Kuo, Yi-Ting Chao, Hsueh-Yung Li, Yi-Ming High-Frequency EDA Laboratory Parallel and Scientific Computing Laboratory Department of Communication Engineering National Chiao Tung University Hsinchu 300 Taiwan

No abstract available

ISBN: (纸本)1424408776

No abstract available

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Energy band calculation of Si/Si0.7Ge0.3Nanopillars in k→space

Energy band calculation of Si/Si0.7Ge0.3Nanopillars in k→sp...

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2020 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2020

作者： Chuang, Min-Hui Li, Yiming Parallel and Scientific Computing Laboratory Institute of Communications Engineering National Chiao Tung University Hsinchu City Hsinchu300 Taiwan

ISBN: (纸本)9784863487635

In this work, we explore the energy band of the well-aligned silicon (Si) nanopillars (NPs) embedded in Si0.7Ge0.3 matrix fabricated by neutral beam etching. Instead of real-space modeling, we formulate and solve the Schrödinger equation with an effective mass approach using 3D finite-element simulation in k→ space. This approach enables us to calculate the electronic structure in a computationally effective manner. The effects of the height, radius, separation, and shape of Si NPs on the energy band and density of states are calculated and discussed. The effect of the radius on the electron energy band control is significant while that of the shape is marginal owing to high geometry aspect ratio. In contrast with the results of electrons, both the radius and separation play crucial role in tuning the energy band of holes;consequently, they govern the variation of energy band gap of Si/Si0.7Ge0.3 NPs. © 2020 The Japan Society of Applied Physics.

关键词： Silicon

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Compact Model Build Upon Dynamic Weighting Artificial Neural Network Approach for Complementary Field Effect Transistors

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IEEE Transactions on Electron Devices 2024年第1期71卷 246-253页

作者： Butola, Rajat Li, Yiming Kola, Sekhar Reddy National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan Institute of Pioneer Semiconductor Innovation The Institute of Artificial Intelligence Innovation National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program The Institute of Communications Engineering the Institute of Biomedical Engineering Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan

In this work, a dynamic weighting-artificial neural network (DW-ANN) methodology is presented for quick and automated compact model (CM) generation. It takes advantage of both TCAD simulations for high accuracy and SPICE simulations for cost-effectiveness. This methodology is developed for gate-all-around (GAA) silicon (Si) nanosheet (NS) complementary field effect transistor (CFET), a potential candidate for future CMOS technology due to its innate properties. The critical process variation (PV) sources that severely degrade the CFET performance are estimated using DW-ANN. It reduces the computation cost and predicts the effects of PV sources with less than 1% error. Furthermore, a compact DW-ANN-based Verilog-A model has been developed that captures the dc as well as transient behavior accurately for circuit-level analysis. CFET-based circuits such as inverter, 6T-static random access memory (SRAM), and ring oscillator (RO) are characterized and implemented using DW-ANN-based CM. The overall average error of the model is reported as less than 2%. Therefore, the proposed device and circuit modeling approach provides a feasible solution for the rapid compact modeling of new emerging devices with good convergence and high accuracy. © 1963-2012 IEEE.

关键词： Neural networks

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Drain-induced-barrier lowering and subthreshold swing fluctuations in 16-nm-gate bulk FinFET devices induced by random discrete dopants

Drain-induced-barrier lowering and subthreshold swing fluctu...

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70th Device Research Conference, DRC 2012

作者： Su, Hsin-Wen Li, Yiming Chen, Yu-Yu Chen, Chieh-Yang Chang, Han-Tung Parallel and Scientific Computing Laboratory Department of Electrical Engineering National Chiao Tung University 1001 Ta-Hsueh Road Hsinchu 300 Taiwan

ISBN: (纸本)9781467311618

Management of process variation and random fluctuation is one of severe challenges in scaling down silicon-based devices continuously according to Moore's law. Emerging fluctuation sources [13] consists of the most critical random dopant fluctuation (RDF) which degrade device characteristic significantly. Unfortunately, recent studies on RDDs were reported for SOI FinFETs [1,5,8]. In this work, we for the first time statistically study characteristic fluctuation of 16-nm-gate high-/metal gate (HKMG) bulk FinFETs with different aspect ratios (AR = 1 and 2;AR = Hfin/W fin) by random-discrete-dopants (RDDs) inside silicon fin channel, based upon our recent simulation studies [1-2,4-7]. Randomly generated devices with three-dimensional (3D) RDDs inside device channel is incorporated into quantum-mechanically corrected 3D device simulation. We compared the DC characteristics for planar and bulk FinFET devices. For the N-type bulk FinFET with AR = 2, it has higher Ion and lower Ioff, further more the fluctuation of Ion and Ioff are both smaller than the results of planar one, and the fluctuation of threshold voltage (σVth) is 46.2 mV for the simulated N-MOSFETs which is significantly reduced to 22.9 mV for the bulk FinFET with AR = 2. We also discuss drain induced barrier lowering (DIBL) and subthreshold swing (S.S) for all devices, and the AR2 FinFET possesses the best performance no matter for the DIBL or S.S effects. There is 68.7% improvement on DIBL and 30.1% improvement on S.S from the planar [1,5,7-8] to AR2 FinFET. The findings of this study indicate that there is a relation between DIBL and RDD's position in which they are near or away from the silicon fin channel surface. It explains the different fluctuation magnitudes of the degraded DIBL effect on devices with the same number of RDDs. © 2012 IEEE.

关键词： FinFET

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Statistical Device Simulation and Machine Learning of Process Variation Effects of Vertically Stacked Gate-All-Around Si Nanosheet CFETs

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IEEE Transactions on Nanotechnology 2024年 23卷 386-392页

作者： Kola, Sekhar Reddy Li, Yiming Butola, Rajat National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Department of Electronics and Electrical Engineering Institute of Communications Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Biomedical Engineering Institute of Pioneer Semiconductor Innovation Institute of Artificial Intelligence Innovation Hsinchu300093 Taiwan

In this study, we report the process variation effect (PVE) including the work function fluctuation (WKF) on the DC/AC characteristic fluctuation of stacked gate-all-around silicon complementary field-effect transistors (CFETs). The PVE affects characteristic fluctuation significantly;in particular, for the variability of off-state current. Owing to the bottom channel of a fin-type, the P-FET suffers from the worst off-state current fluctuation (more than 200% variation) compared to the N-FET. The device variability induced by the WKF is marginal because of amorphous-type metal grains. As input features to an artificial neural network (ANN) model, low and high work function values, as well as parameters of PVE that have prevalent effects on CEFT transfer characteristics are further considered and modeled. The estimated values of R2-score prove that the ANN model properly grasps information from the dataset successfully;thus, it can be used to model emerging CFETs for circuit simulation. © 2002-2012 IEEE.

关键词： Neural networks

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Multiobjective evolutionary approach to silicon solar cell design optimization

Multiobjective evolutionary approach to silicon solar cell d...

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5th Asia Symposium on Quality Electronic Design, ASQED 2013

作者： Huang, Wen-Tsung Chen, Chieh-Yang Chen, Yu-Yu Hsu, Sheng-Chia Li, Yiming Parallel and Scientific Computing Laboratory Department of Electrical and Computer Engineering National Chiao Tung University 1001 Ta-Hsueh Road Hsinchu 300 Taiwan

ISBN: (纸本)9781479913145

In this study, we implement a device simulation-based multi-objective evolutionary algorithm (MOEA) for the optimal design of silicon solar cells. The short-circuited current, the open-circuited voltage, and the conversion efficiency are calculated and used to evaluate the fitness score and access the evolutionary quality of designing parameters via the implemented non-dominating sorting genetic algorithm in the unified optimization framework. Designing parameters, the material and structural parameters are simultaneously optimized for the explored solar cells. Our device simulation-based MOEA methodology is useful, compared with the conventional genetic algorithm, in the solar cell design optimization. © 2013 IEEE.

关键词： Thin film solar cells

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