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Random-dopant-induced variability in nano-CMOS devices and digital circuits

IEEE Transactions on Electron Devices 2009年第8期56卷 1588-1597页

作者： Li, Yiming Hwang, Chih-Hong Li, Tien-Yeh Department of Communication Engineering National Chiao Tung University Hsinchu 300 Taiwan National Nano Device Laboratories Hsinchu 300 Taiwan Parallel and Scientific Computing Laboratory Department of Communication Engineering National Chiao Tung University Hsinchu 300 Taiwan

The impact of the number and position of discrete dopants on device characteristics is crucial in determining the transient behavior of nanoscale circuits. An experimentally validated coupled device-circuit simulation was conducted to investigate the discrete-dopant-induced timing-characteristic fluctuations in 16-nm-gate CMOS circuits. The random-doping effect may induce 18.9% gate-capacitance fluctuation, affecting the intrinsic device gate delay and circuit timing. For a 16-nm-gate CMOS inverter, 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in rise time, fall time, low-to-high delay time, and high-to-low delay time are found. The timing fluctuations of nand and nor circuits are increased, as the number of transistors increased. Because of the same number of transistors in circuits, the timing fluctuation of nand and nor are expected to be similar. However, due to the different function and device operation status of circuit, the timing fluctuation is quite different. The function- and circuit-topology-dependent characteristic fluctuations caused by random nature of discrete dopants are found. This paper provides an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale MOS field-effect-transistor circuits. © 2009 IEEE.

关键词： Timing circuits

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Toward full fluctuation analysis of small FETs

Toward full fluctuation analysis of small FETs

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10th International Meeting for Future of Electron Devices, Kansai, IMFEDK 2012

作者： Li, Yiming Cheng, Hui-Wen Parallel and Scientific Computing Laboratory Department of Electrical and Computer Engineering National Chiao Tung University 1001 Ta-Hsueh Road Hsinchu City Hsinchu 300 Taiwan

ISBN: (纸本)9781467308359

We, for the first time, estimate total fluctuation resulting from random dopants, interface traps and work functions using experimentally calibrated 3D statistical device simulation on 16-nm-gate high-κ/metal gate planar and bulk FinFET devices. The total full 3D simulated threshold voltage fluctuation (σVth), induced by the aforementioned random sources simultaneously, is different from their statistical total sum because the assumption of independently and identically distributed random variables is invalid owing to strong surface potential's interactions among them. Structural innovation using bulk FinFET implies significant fluctuation suppression, which is about 45.6% reduction on σVth. 3D vertical channel-based device provides good capability in fluctuation reduction, compared with process efforts on low interface trap density (e.g., Dit is below 10 11 eV-1 cm-2) and small grain size (e.g., 1x1 nm2) of metal gate on planar one. © 2012 IEEE.

关键词： Work function

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The TSTT mesh interface

The TSTT mesh interface

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44th AIAA Aerospace Sciences Meeting 2006

作者： Ollivier-Gooch, Carl Chand, Kyle Dahlgren, Tamara Diachin, Lori Freitag Fix, Brian Kraftcheck, Jason Xiaolin, Li Seol, E. Seegyoung Shephard, Mark S. Tautges, Timothy Trease, Harold Advanced Numerical Simulation Laboratory University of British Columbia Center for Applied Scientific Computing Lawrence Livermore National Laboratory Dept. of Applied Mathematics and Statistics SUNY Stonybrook Parallel Computing Sciences Sandia National Laboratories Scientific Computation Research Center Rensselaer Polytechnic Institute Pacific Northwest National Laboratory

ISBN: (纸本)1563478072

PDE-based numerical simulation applications commonly use basic software infrastructure to manage mesh, geometry, and discretization data. The commonality of this infrastructure implies the software is theoretically amenable to re-use. However, the traditional reliance on library-based implementations of these functionalities hampers experimentation with different software instances that provide similar functionality. This is especially true for meshing and geometry libraries where applications often directly access the underlying data structures, which can be quite different from implementation to implementation. Thus, using different libraries interchangeably or interoperably for this functionality has proven difficult at best and has hampered the wide spread use of advanced meshing and geometry tools developed by the research community. To address these issues, the Terascale Simulation Tools and Technologies center is working to develop standard interfaces to enable the creation of interoperable and interchangeable simulation tools. In this paper, we focus on a language-and data-structure-independent interface supporting query and modification of mesh data conforming to a general abstract data model. We describe the model and interface, and provide programming "best practices" recommendations based on early experience implementing and using the interface.

关键词： Software engineering

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Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors

IEEE Open Journal of Nanotechnology

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IEEE Open Journal of Nanotechnology 2023年 4卷 229-238页

作者： Kola, Sekhar Reddy Li, Yiming National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan Parallel and Scientific Computing Laboratory National Yang Ming Chiao Tung University Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Communications Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Biomedical Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan

Characteristic variability induced by process variation effect (PVE) is one of technological challenges in semiconductor industry. In this work, we computationally study electrical characteristic and power fluctuations induced by six factors of PVE of the gate-all-around (GAA) silicon (Si) nanosheet (NS) complementary field-effect-transistors (CFETs) which are formed by vertically stacking n-FET on top of p-FET. Among the six factors, NS thickness (TNS), NS width (WNS), and gate length (LG) are identified as crucial factors contributing to large variations in device characteristics. The p-FET exhibits substantial off-state current fluctuation (about 151%) due to the bottom parasitic channel leakages. Compared with the magnitudes of dynamic and short circuit powers, the static power is marginal, but it possesses the largest fluctuation (up to 148%). If we assume that each factor of PVE has the same probability distribution as the others and all are mutually independent, the statistical sum of their power fluctuations will exhibit more than 50% overestimations, compared with the results when all factors are considered simultaneously. © 2020 IEEE.

关键词： III-V semiconductors

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On characteristic fluctuation of nonideal bulk FinFET devices

On characteristic fluctuation of nonideal bulk FinFET device...

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IEEE International Nanoelectronics Conference (INEC)

作者： Yiming Li Wen-Tsung Huang Parallel and Scientific Computing Laboratory National Chaio Tung University

This work, for the first time, estimates the random dopant fluctuation (RDF) on DC characteristics of trapezoidal bulk FinFET devices by using an experimentally calibrated 3D quantum-mechanically corrected device simulation. For bulk FinFET devices under the same channel volume, we analyze the impact of geometry variation and RDF on the threshold voltage, the on-/off-state current with respect to different channel fin angles. The channel fin angle increases, the on-state current increases owing to increase of total fin width, but small- and large-fin-angle devices have comparable RDF. The threshold voltage is affected to different extents by RDs appearing in the upper and lower channel fin regions. Two major factors, the total fin width and the RD's position, affecting the V th fluctuation of RDF are discussed.

关键词： FinFETs Fluctuations Resource description framework Logic gates Semiconductor process modeling Three-dimensional displays Threshold voltage

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Statistical device simulation of intrinsic parameter fluctuation in 16-nm-gate n- and p-type Bulk FinFETs

Statistical device simulation of intrinsic parameter fluctua...

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IEEE Conference on Nanotechnology

作者： Yu-Yu Chen Wen-Tsung Huang Sheng-Chia Hsu Han-Tung Chang Chieh-Yang Chen Chin-Min Yang Li-Wen Chen Yiming Li Department of Electrical and Computer Engineering Parallel and Scientific Computing Laboratory Taiwan

In this paper, we estimate the influence of random dopants (RDs), interface traps (ITs), and random work functions (WKs) using the experimentally calibrated 3D device simulation on DC characteristic of high-κ / metal gate n- and p-type bulk fin-typed field-effect-transistors. We further study these intrinsic parameter fluctuations' impact on drain induced barrier lowering (DIBL). The main findings of this work show the RDF and WKF on n-type device are larger than that of p-type one. The DIBL is dominated by the number of random dopants.

关键词： Fluctuations FinFETs Resource description framework Logic gates Metals Semiconductor process modeling Three-dimensional displays

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Enhancing the Performance of E-Mode AlGaN/GaN HEMTs With Recessed Gates Through Low-Damage Neutral Beam Etching and Post-Metallization Annealing

IEEE Open Journal of Nanotechnology

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IEEE Open Journal of Nanotechnology 2023年 4卷 150-155页

作者： Chen, Yi-Ho Ohori, Daisuke Aslam, Muhammad Lee, Yao-Jen Li, Yiming Samukawa, Seiji National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Graduate Degree Program of College of Electrical and Computer Engineering Hsinchu300093 Taiwan Tohoku University Institute of Fluid Science Sendai980-8577 Japan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Electrical Engineering and Computer Science International Graduate Program Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Pioneer Semiconductor Innovation Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Institute of Communications Engineering Institute of Biomedical Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan National Yang Ming Chiao Tung University Institute of Communications Engineering Hsinchu300093 Taiwan

This study investigated the electrical properties of AlGaN/GaN high-electron-mobility transistors (HEMTs) with varied recess depths under the gate electrode. We demonstrated a recess depth of approximately 6 nm, which was achieved through neutral beam etching (NBE) technique with a low etch rate of 1.8 nm/min, resulting in device enhancement-mode (E-mode) behavior with threshold voltage (Vth) of 0.49 V. The effects of post-metallization annealing (PMA) on the device performance were also examined. The results revealed that PMA treatment improves the DC characteristics of the devices, including maximum drain current (IDMAX), transconductance (gm), subthreshold swing (SS), on-off ratio, and off-state leakage current, with maximum enhancement percentage of 18.3% for IDMAX, 3758% for on-off ratio, and 54.3% for SS. Moreover, this study compared the recess depths of metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) with the SiN dielectric layer. The results showed that MIS-HEMTs exhibit more negative Vth values, which can be attributed to the controlled surface states achieved through passivation. © 2020 IEEE.

关键词： Etching

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Automatic generation of passive equivalent circuits for broadband microstrip antennas

Automatic generation of passive equivalent circuits for broa...

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2007 IEEE Antennas and Propagation Society International Symposium, AP-S

作者： Kuo, Yi-Ting Chao, Hsueh-Yung Li, Yiming High-Frequency EDA Laboratory Department of Communication Engineering National Chiao Tung University Hsinchu 300 Taiwan Parallel and Scientific Computing Laboratory Department of Communication Engineering National Chiao Tung University Hsinchu 300 Taiwan

No abstract available

ISBN: (纸本)1424408776

No abstract available

关键词：

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Simulation study on electrical characteristic of AlGaN/GaN high electron mobility transistors with AlN spacer layer

Simulation study on electrical characteristic of AlGaN/GaN h...

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作者： Shrestha, Niraj Man Li, Yiming Chang, Edward Yi Compound Semiconductor Device Laboratory Department of Material Science and Engineering National Chiao Tung University Hsinchu 300 Taiwan Parallel and Scientific Computing Laboratory Department of Electrical and Computer Engineering National Chiao Tung University Hsinchu 300 Taiwan

Two-dimensional electron gas (2DEG) property is crucial for the performance of GaN-based high electron mobility transistors (HEMTs). The 2DEGrelated concentration and mobility can be improved as device's performance booster. Electrical characteristics of AlGaN/AlN/GaN HEMT are numerically simulated and compared with conventional AlGaN/GaN HEMT. The main findings of this study indicate that 2DEG's concentration level is increased when a spacer layer of AlN in the interface of AlGaN/AlN/GaN is inserted owing to large conduction band off set, high polarization field, and high barrier. Notably, when a thin spacer layer of AlN is introduced, the 2DEG's distribution virtually shifts away from the interface which reduces the interface scattering. The scattering appearing in conventional AlGaN/GaN HEMT includes alloy and interface roughness scatterings. They are reduced in AlGaN/AlN/GaN HEMT due to binary nature of AlN material. A critical thickness of spacer layer for mobility is 0.5nm and the maximum drain current and transconductance (Gm) are at 1.5 and 1.2nm thickness of AlN spacer layer. Increasing thickness of AlN spacer layer deteriorates the ohmic resistance of source/drain contact and hence degrades the performance of device beyond 1.5-nm-thick AlN spacer layer. © 2014 The Japan Society of Applied Physics.

关键词： Aluminum nitride

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Characteristic Variability of GAA Si NS CFETs Induced by Process Variation Effect and Intrinsic Parameter Fluctuation

Characteristic Variability of GAA Si NS CFETs Induced by Pro...

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International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

作者： Min-Hui Chuang Sekhar Reddy Kola Yiming Li Institute of Communications Engineering and Parallel and Scientific Computing Laboratory National Yang Ming Chiao Tung Univeristy Hsinchu Taiwan Parallel and Scientific Computing Laboratory National Yang Ming Chiao Tung Univeristy Hsinchu Taiwan

ISBN: (数字)9798331516352

ISBN: (纸本)9798331516369

We simultaneously estimate impacts of process variation effect (PVE) consisting of three major variations and intrinsic parameter fluctuation (IPF) including two crucial random factors on electrical characteristics of gate-all-around silicon nanosheet complementary field-effect transistors (GAA Si NS CFETs). The combined influence of PVE and IPF on both N-/P-FETs in GAA Si NS CFETs results in significant fluctuation of the off-state current. This variability to PVE factors is particularly pronounced in the P-type device due to the parasitic nature of its bottom channel. Furthermore, compared with the magnitudes of dynamic and short circuit powers, the static power is marginal, but it possesses the largest fluctuation (about RSD of 82%). Notably, the statistical sum of each factors of fluctuation overestimates the total variability owing to ignoring the correlation effects among all random factors, compared with the full estimation at the same time.

关键词： Fluctuations Correlation Gallium arsenide Estimation Logic gates Electric variables Silicon Transistors

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