检索结果-内蒙古大学图书馆

IEEE Conference on Nanotechnology

作者： Sekhar Reddy Kola Yiming Li Narasimhulu Thoti Parallel and Scientific Computing Laboratory EECS International Graduate Program from National Chiao Tung University Hsinchu 300 Taiwan Parallel and Scientific Computing Laboratory Institute of Communications Engineering National Chiao Tung University Hsinchu 300 Taiwan Parallel and Scientific Computing Laboratory EECS International Graduate Program National Chiao Tung University Hsinchu 300 Taiwan

ISBN: (数字)9781728182643

ISBN: (纸本)9781728182650

We report the effects of the spacer and the single-charge trap (SCT) on the voltage transfer characteristics of cylindrical-shape gate-all-around (GAA) silicon (Si) nanowire (NW) metal-oxide-semiconductor field effect transistor (MOSFETs). We explore the impact of low-x spacer, high-x spacer, and dual spacer (DS) on electrical characteristics of the GAA Si NW MOSFET with a gate length of 10 nm. Compared with the nominal device (i.e., the device without spacer), the device with DS possesses 68.8% reduction on the normalized off-current and 29.4% increase on the normalized on-current for n- and p-type devices. Similarly, 21.1% and 3.38% improvements on the normalized high and low noise margins can be achieved for the GAA Si NW complementary metal-oxide-semiconductor (CMOS) circuit. Notably, the voltage transfer characteristics induced by the acceptor- and donor-type SCT for the CMOS circuit with DS possesses 2.64% and 3.82% enhancements for the normalized high and low noise margins compared with the nominal one.

关键词： Silicon Gallium arsenide Logic gates MOSFET Semiconductor device modeling Hafnium compounds Numerical models

来源：评论

学校读者我要写书评

暂无评论

Nanosized-Metal-Grain-Pattern-Dependent Threshold-Voltage Models for the Vertically Stacked Multichannel Gate-All-Around Si Nanosheet MOSFETs and Their Applications in Circuit Simulation

引用

IEEE Transactions on Electron Devices 2024年第1期71卷 350-358页

作者： Sung, Wen-Li Li, Yiming Chuang, Min-Hui National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Institute of Communications Engineering Department of Electronics and Electrical Engineering Hsinchu300093 Taiwan Institute of Biomedical Engineering Institute of Pioneer Semiconductor Innovation Institute of Artificial Intelligence Innovation National Yang Ming Chiao Tung University Hsinchu300093 Taiwan

This article proposes grain-pattern-dependent threshold-voltage ( Vth ) models to predict the variability of Vth ( Vth ) due to work-function (WK) fluctuation (WKF) for the vertically stacked multichannel gate-all-around (GAA) silicon (Si) nanosheet (NS) MOSFETs (NS-FETs). In addition, the models were applied to estimate the variability of static noise margin (SNM) of a 6-T SRAM, a CMOS inverter, and a single-stage common-source amplifier. To model this phenomenon, each perturbed local metal grain is counted by the superposition principle statistically. The model can be used to explain the values of Vth by the location effect of metal grain for the vertically stacked multichannel devices. In addition, the model can predict the values of Vth for the vertically stacked multichannel devices with different metal grain sizes. Compared with the results of 3-D device simulation (3D-DS), the error rate (ER) of our model prediction is less than 0.5%. According to the formulated model, an empirical expression is further advanced, which has continuous derivatives and can be easily incorporated into a circuit simulator to assess the variability of SNM of a 6-T SRAM, CMOS inverter, and single-stage common-source amplifier affected by the WKF, where the ERs are below 0.5%. The proposed models provide a valuable approach for estimating the impact of circuit design by the WKF. © 1963-2012 IEEE.

关键词： III-V semiconductors

来源：评论

学校读者我要写书评

暂无评论

Compact Modeling of N- and P-Type GAA NS FETs Using Physical-Based Artificial Neural Networks with Temperature Dependence

Compact Modeling of N- and P-Type GAA NS FETs Using Physical...

引用

International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

作者： Yun Dei Ya-Shu Yang Yiming Li Institue of Biomedical Engineering and Parallel and Scientific Computing Laboratory National Yang Ming Chiao Tung Univeristy Hsinchu Taiwan Institue of Communications Engineering and Parallel and Scientific Computing Laboratory National Yang Ming Chiao Tung Univeristy Hsinchu Taiwan

We propose a compact model that utilizes physical-based artificial neural networks (ANNs) to model the effect of temperature on n- and p-type gate-all-around nanosheet FETs. Our compact model comprises two independent ANNs, where the first ANN is designed to output parameters related to temperature and the second ANN is utilized for the device physical parameters. All outputs of ANNs are integrated into a physical equation of drain current to form the entire compact model. Compared with the BSIM-CMG model in circuit simulations, our results are highly consistent in transfer characteristics and timing dynamics.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Drain-induced-barrier lowering and subthreshold swing fluctuations in 16-nm-gate bulk FinFET devices induced by random discrete dopants

Drain-induced-barrier lowering and subthreshold swing fluctu...

引用

Device Research Conference

作者： Hsin-Wen Su Yiming Li Yu-Yu Chen Chieh-Yang Chen Han-Tung Chang Parallel and Scientific Computing Laboratory Department of Electrical Engineering National Chiao Tung University Hsinchu Taiwan

Management of process variation and random fluctuation is one of severe challenges in scaling down silicon-based devices continuously according to Moore's law. Emerging fluctuation sources [1-3] consists of the most critical random dopant fluctuation (RDF) which degrade device characteristic significantly. Unfortunately, recent studies on RDDs were reported for SOI FinFETs [1,5,8]. In this work, we for the first time statistically study characteristic fluctuation of 16-nm-gate high-κ/metal gate (HKMG) bulk FinFETs with different aspect ratios (AR = 1 and 2; AR = H fin /W fin ) by random-discrete-dopants (RDDs) inside silicon fin channel, based upon our recent simulation studies [1-2,4-7]. Randomly generated devices with three-dimensional (3D) RDDs inside device channel is incorporated into quantum-mechanically corrected 3D device simulation. We compared the DC characteristics for planar and bulk FinFET devices. For the N-type bulk FinFET with AR = 2, it has higher I on and lower I off , further more the fluctuation of I on and I off are both smaller than the results of planar one, and the fluctuation of threshold voltage (σV th ) is 46.2 mV for the simulated N-MOSFETs which is significantly reduced to 22.9 mV for the bulk FinFET with AR = 2. We also discuss drain induced barrier lowering (DIBL) and subthreshold swing (S.S) for all devices, and the AR2 FinFET possesses the best performance no matter for the DIBL or S.S effects. There is 68.7% improvement on DIBL and 30.1% improvement on S.S from the planar [1,5,7-8] to AR2 FinFET. The findings of this study indicate that there is a relation between DIBL and RDD's position in which they are near or away from the silicon fin channel surface. It explains the different fluctuation magnitudes of the degraded DIBL effect on devices with the same number of RDDs.

关键词： FinFETs Metals Logic gates

来源：评论

学校读者我要写书评

暂无评论

Characteristic fluctuation of gate-all-around silicon nanowire MOSFETs induced by random discrete dopants from source/drain extensions 11

Characteristic fluctuation of gate-all-around silicon nanowi...

引用

11th Annual TechConnect World Innovation Conference and Expo, Held Jointly with the 20th Annual Nanotech Conference and Expo, and the 2017 National SBIR/STTR Conference

作者： Sung, Wen-Li Li, Yiming Parallel and Scientific Computing Laboratory National Chiao Tung University Hsinchu Taiwan Institute of Communications Engineering National Chiao Tung University Hsinchu Taiwan Department of Electrical and Computer Engineering National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)9780998878218

In this work, characteristic fluctuation of undoped gate-all-around silicon nanowire MOSFETs induced by random discrete dopants (RDDs) penetrating from the source/drain (S/D) extensions is explored. Compared with the results of RDDs penetrating from the S extension, asymmetric variations of characteristics induced by RDDs penetrating from the D extension are suppressed owing to the different extent of screening effect on the surface of channel;in particular, the fluctuations of voltage gain and cut-off frequency are reduced from 24% and 21% to 7% and 10%, respectively, because of the effective fluctuation reduction of maximum transconductance near the D extension.

关键词： Nanowires

来源：评论

学校读者我要写书评

暂无评论

Electrical characteristic of InGaAs multiple-gate MOSFET devices

Electrical characteristic of InGaAs multiple-gate MOSFET dev...

引用

International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

作者： Cheng-Hao Huang Yiming Li Parallel and Scientific Computing Laboratory and Institute of Communications Engineering National Chiao Tung University Hsinchu Taiwan

In this work, we study the impact of channel fin width (W fin ) and fin height (H fin ) on III-V multiple-gate metal-oxide-semiconductor field-effect transistors (MOSFETs). We numerically simulated the output and transfer characteristics and the short-channel effect (SCE) of 14-nm InGaAs triple-gate MOSFETs by using an experimentally validated simulation. The engineering findings of this study indicate that devices with W fin = 10 nm and H fin between 14 and 21 nm possess optimal characteristic owing to a tradeoff between the drain-induced barrier lowing and subthreshld property. The effects of channel resistance, effective width, and quantum confinement resulting from the H fin -dependent small energy band gap channel film on device characteristic are further estimated and discussed.

关键词： MOSFET Indium gallium arsenide Resistance Logic gates III-V semiconductor materials Potential well

来源：评论

学校读者我要写书评

暂无评论

DC/AC/RF Characteristics of Multi-Channel GAA NS FETs with ML and BL MoS2

DC/AC/RF Characteristics of Multi-Channel GAA NS FETs with M...

引用

International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

作者： Yueh-Ju Chan Sekhar Reddy Kola Yiming Li Institute of Communications Engineering and Parallel and Scientific Computing Laboratory National Yang Ming Chiao Tung Univeristy Hsinchu Taiwan EECS International Graduate Program and Parallel and Scientific Computing Laboratory National Yang Ming Chiao Tung Univeristy Hsinchu Taiwan

For the first time, we examine the performance of gate-all-around nanosheet field effect transistor (GAA NS FET) with both monolayer (ML) and bilayer (BL) molybdenum disulfide (MoS 2 ). As compared to the control sample of silicon (Si), MoS 2 devices exhibit reduced short-channel effects (SCE) owing to its larger band gap and larger effective mass. The GAA NS FET with BL MoS 2 possesses moderate energy bandgap and large channel thickness which exhibits superior on state current and voltage gain.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Characteristics of Gate-All-Around Silicon Nanowire and Nanosheet MOSFETs with Various Spacers

Characteristics of Gate-All-Around Silicon Nanowire and Nano...

引用

International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

作者： Sekhar Reddy Kola Yiming Li- Narasimhulu Thoti Parallel and Scientific Computing LaboratoryEECS International Graduate ProgramInstitute of Communications Engineering Parallel and Scientific Computing Laboratory1001 Ta-Hsueh Rd. National Chiao Tung University Hsinchu Taiwan Institute of Communications Engineering

ISBN: (数字)9784863487635

ISBN: (纸本)9781728173542

We estimate DC characteristics and single-charge trap (SCT) induced random telegraph noise (RTN) of gate-all-around (GAA) silicon nanowire (NW) and nanosheet (NS) metal-oxide-semiconductor field effect transistor (MOSFETs) for sub-5-nm nodes. Devices with various dielectric spacers from low- to high-κ including asymmetric dual spacers (ADS) are considered. More than 31% boost on the normalized on-state currents is observed for the explored devices with high-κ and ADS spacers. Similarly, for the normalized off-state currents, more than 50% reduction is achieved. The largest magnitude of the RTN (ΔI D /I D ×100%) is 6.7% for the nominal GAA Si NS MOSFET with an effective channel width of 40-nm.

关键词： MOSFET Shape Gallium arsenide Logic gates Silicon Semiconductor process modeling Dielectrics

来源：评论

学校读者我要写书评

暂无评论

Energy Band Calculation of Si/Si0.7 Ge0.3 Nanopillars in k➙ Space

Energy Band Calculation of Si/Si0.7 Ge0.3 Nanopillars in k➙...

引用

International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

作者： Min-Hui Chuang Yiming Li Parallel and Scientific Computing Laboratory Institute of Communications Engineering National Chiao Tung University Hsinchu City Taiwan

ISBN: (数字)9784863487635

ISBN: (纸本)9781728173542

In this work, we explore the energy band of the well-aligned silicon (Si) nanopillars (NPs) embedded in Si 0.7 Ge 0.3 matrix fabricated by neutral beam etching. Instead of real-space modeling, we formulate and solve the Schrodinger equation with an effective mass approach using 3D finite-element simulation in ⃗k space. This approach enables us to calculate the electronic structure in a computationally effective manner. The effects of the height, radius, separation, and shape of Si NPs on the energy band and density of states are calculated and discussed. The effect of the radius on the electron energy band control is significant while that of the shape is marginal owing to high geometry aspect ratio. In contrast with the results of electrons, both the radius and separation play crucial role in tuning the energy band of holes; consequently, they govern the variation of energy band gap of Si/Si 0.7 Ge 0.3 NPs.

关键词：

来源：评论

学校读者我要写书评

暂无评论

3D simulation of morphological effect on reflectance of Si3N4 subwavelength structures for silicon solar cells

引用

Nanoscale Research Letters 2012年第1期7卷 196-196页

作者： Li, Yiming Lee, Ming-Yi Cheng, Hui-Wen Lu, Zheng-Liang Parallel and Scientific Computing Laboratory Department of Electrical Engineering National Chiao Tung University 1001 Ta-Hsueh Road Hsinchu 300 Taiwan

In this study, we investigate the reflectance property of the cylinder, right circular cone, and square pyramid shapes of silicon nitride (Si3N4) subwavelength structure (SWS) with respect to different designing parameters. In terms of three critical factors, the reflectance for physical characteristics of wavelength dependence, the reflected power density for real power reflection applied on solar cell, and the normalized reflectance (reflected power density/incident power density) for real reflectance applied on solar cell, a full three-dimensional finite element simulation is performed and discussed for the aforementioned three morphologies. The result of this study shows that the pyramid shape of SWS possesses the best reflectance property in the optical region from 400 to 1000 nm which is useful for silicon solar cell applications. © 2012 Li et al.

关键词： Silicon solar cells

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：