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2020 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2020

作者： Lee, Yu-Chun Kola, Sekhar Reddy Chen, Chieh-Yang Chuang, Min-Hui Li, Yiming Parallel and Scientific Computing Laboratory Institute of Biomedical Engineering Institute of Communications Engineering Eecs International Graduate Program Department of Electrical and Computer Engineering Center for MmWave Smart Radar System and Technologies National Chiao Tung University 1001 Ta-Hsueh Rd Hsinchu300 Taiwan

ISBN: (纸本)9781728142326

In this work, our study comprises of design and investigation on negative capacitance (NC), metal-oxide-semiconductor (MOS) field effects transistors (MOSFETs) with spacer and source/drain (S/D) overlap engineering. The scope of the work is to boost the performance and high-energy efficiency of the studied NC-MOSFETs by using the ferro electric material (FE). The NC-MOSFETs with the spacer technology can achieve the admirable Ion/Ioff ratio and subthreshold swing (SS), compared with planar MOSFETs. It makes device scaling possible by eliminating the short channel effect (SCE). We further estimated the effect of FE thickness and spacer, which are another critical parameter of obtaining better electrical characteristics and reducing SS. © 2020 IEEE.

关键词： Capacitance

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Automatic Instrumentation Refinement for Empirical Performance Modeling

Automatic Instrumentation Refinement for Empirical Performan...

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IEEE/ACM International Workshop on Programming and Performance Visualization Tools (ProTools)

作者： Jan-Patrick Lehr Alexandru Calotoiu Christian Bischof Felix Wolf Institute for Scientific Computing Technische Universität Darmstadt Darmstadt Germany Laboratory for Parallel Programming Technische Universität Darmstadt Darmstadt Germany

ISBN: (纸本)9781728160276

The analysis of runtime performance is important during the development and throughout the life cycle of HPC applications. One important objective in performance analysis is to identify regions in the code that show significant runtime increase with larger problem sizes or more processes. One approach to identify such regions is to use empirical performance modeling, i.e., building performance models based on measurements. While the modeling itself has already been streamlined and automated, the generation of the required measurements is time consuming and tedious. In this paper, we propose an approach to automatically adjust the instrumentation to reduce overhead and focus the measurements to relevant regions, i.e.,such that show increasing runtime with larger input parameters or increasing number of MPI ranks. Our approach employs Extra-P to generate performance models, which it then uses to extrapolate runtime and, finally, decide which functions should be kept for measurement. Also, the analysis expands the instrumentation, by heuristically adding functions based on static source-code features. We evaluate our approach using benchmarks from SPEC CPU 2006, SU2, and parallel MILC. The evaluation shows that our approach can filter functions of little interest and generate profiles that contain mostly relevant regions. For example, the overhead for SU2 can be improved automatically from 200% to 11% compared to filtered Score-P measurements.

关键词： Instruments Runtime Mathematical model Analytical models Atmospheric measurements Particle measurements parallel processing

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A Nanosized-Metal-Grain Pattern-Dependent Model for Work-Function Fluctuation of Gate-All-Around Silicon Nanofin and Nanosheet MOSFETs

A Nanosized-Metal-Grain Pattern-Dependent Model for Work-Fun...

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2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022

作者： Sung, Wen-Li Li, Yiming National Yang Ming Chiao Tung University Parallel and Scientific Computing Laboratory Hsinchu300 Taiwan National Yang Ming Chiao Tung University Institute of Communications Engineering Hsinchu300 Taiwan National Yang Ming Chiao Tung University Department of Electrical and Computer Engineering Hsinchu300 Taiwan

ISBN: (纸本)9781665409230

A nanosized-metal-grain pattern-dependent model was proposed for work-function-fluctuation (WKF)-induced variability on the gate-all-around (GAA) silicon nanofin and nanosheet MOSFET (NF-FET and NS-FET). This model was developed by the perturbation of location metal grains with error correction (EC) and was validated by the 3D device simulation (3D-DS) with 5000 samples in low errors (error rate (ER) © 2022 IEEE.

关键词： Nanosheets

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Experimentally effective clean process to C-V characteristic variation reduction of HKMG MOS devices

Experimentally effective clean process to C-V characteristic...

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IEEE Conference on Nanotechnology

作者： Chien-Hung Chen Yiming Li Chieh-Yang Chen Yu-Yu Chen Sheng-Chia Hsu Wen-Tsung Huang Sheng-Yuan Chu Department of Electrical Engineering National Cheng-Kung University Tainan Taiwan Department of Electrical and Computer Engineering Parallel and Scientific Computing Laboratory Hsinchu Taiwan

ISBN: (纸本)9781479906741

In this work, the planar HKMG MOS devices are fabricated on (100) wafer with p-substrate. To improve the samples' interface roughness between the Si/Ge film and the interface layer, three different clean treatments are considered to fabricate the MOS devices. Among processes, the experiment indicates that HF and water rinse can present hydrogen termination to bond silicon as a good passivation. The measured C-V curves and HRTEM of the fabricated samples show the interface roughness is improved significantly. The extracted shift of flat band voltage (ΔV fb ) and density of interface traps (D it ) have around 50% improvement.

关键词： Silicon Capacitance-voltage characteristics Surface cleaning Rough surfaces Surface roughness Films

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Teracluster LSSC-II--Its designing principles and applications in large scale numerical simulations

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中国科学A辑（英文版） 2004年第z1期47卷 53-68页

作者： Zhang Linbo Chen Shiyi LI Xinliang CAO Jianwen ZHANG Wensheng GONG Xingao State Key Laboratory of Scientific and Engineering Computing Academy of Mathematics and System Sciences Chinese Academy of Sciences Beijing 100080 China Department of Mechanical Engineering The Johns Hopkins University and Center for Computational Science and Engineering Peking University Beijing 100875 China Institute of Mechanics Chinese Academy of SciencesBeijing 100080 China Parallel Computing Laboratory Institute of Software Chinese Academy of Sciences Beijing 100080 China Academy of Mathematics and System Sciences Chinese Academy of Sciences Beijing 100080 China Surface Physics Laboratory National Key Laboratory Fudan University Shanghai 200433 Institute of Solid State Physics Chinese Academy of Sciences Hefei 230031 China

The teracluster LSSC-II installed at the State Key laboratory of scientific and Engineering computing, Chinese Academy of Sciences is one of the most powerful PC clusters in China. It has a peek performance of 2Tflops. With a Linpack performance of 1.04Tflops, it is ranked at the 43rd place in the 20th TOP500 List (November 2002), 51st place in the 21st TOP500 List (June 2003), and the 82nd place in the 22nd TOP500 List (November 2003) with a new Linpack performance of 1.3Tflops. In this paper, we present some design principles of this cluster, as well as its applications in some large-scale numerical simulations.

关键词： high performance computing PC cluster large scale numerical simulations

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Impact of geometry aspect ratio on 10-nm gate-all-around silicon-germanium nanowire field effect transistors

Impact of geometry aspect ratio on 10-nm gate-all-around sil...

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IEEE Conference on Nanotechnology

作者： Pei-Jung Chao Yiming Li Parallel and Scientific Computing Laboratory National Chaio Tung University Hsinchu Taiwan Department of Electrical and Computer Engineering National Chaio Tung University Hsinchu Taiwan

In this paper, we study electrical characteristics of gate-all-around (GAA) silicon-germanium (SiGe) nanowire field effect transistors (NWFETS) with different aspect ratio (AR) of channel. Device characteristics: the subthreshold swing (SS), the drain induced barrier lowering (DIBL), and the I ON /I OFF ratio are simulated by using three-dimensional quantum mechanically corrected device simulation. Electrical characteristics of 10-nm-gate GAA Si 1-x Ge x NWFET devices are explored with respect to different thickness of SiGe and Ge's mole fraction. It is investigated that an ellipse-shaped channel with a small aspect ratio possesses better DC characteristics, compared with the one which has large AR due to its good gate controllability.

关键词： Logic gates Computational modeling Silicon Mathematical model Field effect transistors Solid modeling Electric variables

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Extreme scale de novo metagenome assembly

arXiv

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arXiv 2018年

作者： Georganas, Evangelos Egan, Rob Hofmeyr, Steven Goltsman, Eugene Arndt, Bill Tritt, Andrew Buluç, Aydın Oliker, Leonid Yelick, Katherine Parallel Computing Lab Intel Corp Computational Research Division Joint Genome Institute Lawrence Berkeley National Laboratory United States National Energy Research Scientific Computing Center United States

Metagenome assembly is the process of transforming a set of short, overlapping, and potentially erroneous DNA segments from environmental samples into the accurate representation of the underlying microbiomes's genomes. State-of-the-art tools require big shared memory machines and cannot handle contemporary metagenome datasets that exceed Terabytes in size. In this paper, we introduce the MetaHipMer pipeline, a high-quality and high-performance metagenome assembler that employs an iterative de Bruijn graph approach. MetaHipMer leverages a specialized scaffolding algorithm that produces long scaffolds and accommodates the idiosyncrasies of metagenomes. MetaHipMer is end-to-end parallelized using the Unified parallel C language and therefore can run seamlessly on shared and distributed-memory systems. Experimental results show that MetaHipMer matches or outperforms the state-of-the-art tools in terms of accuracy. Moreover, MetaHipMer scales efficiently to large concurrencies and is able to assemble previously intractable grand challenge metagenomes. We demonstrate the unprecedented capability of MetaHipMer by computing the first full assembly of the Twitchell Wetlands dataset, consisting of 7.5 billion reads - size 2.6 TBytes. Copyright © 2018, The Authors. All rights reserved.

关键词： Scaffolds

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Random dopant fluctuation in 10-nm-gate multi-channel gate-all-around nanowire field effect transistors

Random dopant fluctuation in 10-nm-gate multi-channel gate-a...

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Nanotechnology 2014: Electronics, Manufacturing, Environment, Energy and Water - 2014 NSTI Nanotechnology Conference and Expo, NSTI-Nanotech 2014

作者： Chang, Han-Tung Li, Yiming Parallel and Scientific Computing Laboratory National Chiao Tung University 1001 Ta-Hsueh Road Hsinchu Taiwan Institute of Communications Engineering National Chiao Tung University 1001 Ta-Hsueh Road Hsinchu Taiwan Department of Electrical and Computer Engineering National Chiao Tung University 1001 Ta-Hsueh Road Hsinchu Taiwan

ISBN: (纸本)9781482258301

This paper, for the first time, studies the random dopant fluctuation (RDF) in the 10-nm-gate multi-channel gate-all-around nanowire field-effect transistors (FETs). A 3D statistically "atomistic" device simulation approach to analyzing random-dopant effects is intensively performed to study device's physical and electrical characteristic fluctuation. The key findings of this study indicate an ellipse-shaped gate-all-around nanowire FETs with relatively smaller aspect ratio of radius possess better DC characteristic, suppression of short-channel effect, and immunity to RDF, compared with large aspect ration one.

关键词： Aspect ratio

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Automatic generation of passive equivalent circuits for broadband microstrip antennas

Automatic generation of passive equivalent circuits for broa...

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Antennas and Propagation Society International Symposium

作者： Yi-Ting Kuo Hsueh-Yung Chao Yiming Li High-Frequency EDA Laboratory Department of Communication Engineering National Chiao Tung University Hsinchu Taiwan Parallel and Scientific Computing Laboratory Department of Communication Engineering National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)9781424408771;1424408776

In this paper, we propose an efficient method for extracting passive equivalent circuits of broadband antennas. To fully automate the extraction, the vector fitting in B. Gustaven and A. Semlyen (1999) is modified such that the order of the rational approximation can be determined automatically for a given error bound. Then, the approximation is corrected by quadratic programming for enforcing passivity. The passive model is further synthesized by RLC components using algorithms in G. Antonini (2003). As a result, simulated or measured frequency responses of a broadband antenna can be fit with minimum fitting error over a wide range of frequencies.

关键词： Microstrip antennas Broadband antennas Equivalent circuits Dipole antennas Frequency Microstrip components Laboratories Radiofrequency integrated circuits Circuit simulation Antenna accessories

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Optimization of physics-based equivalent circuits for microstrip patch antennas

Optimization of physics-based equivalent circuits for micros...

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Antennas and Propagation Society International Symposium

作者： Tang-Jung Chiu Yi-Ting Kuo Hsueh-Yung Chao Yi-Ming Li High-Frequency EDA Laboratory Department of Communication Engineering National Chiao Tung University Hsinchu Taiwan Parallel and Scientific Computing Laboratory Department of Communication Engineering National Chiao Tung University Hsinchu Taiwan

ISBN: (纸本)1424408776;97

While many commercial EDA tools already have the capability to synthesize networks by evolutionary and statistical algorithms, we gain a lot of physical insight when the network synthesis problem is solved by gradient-based local optimization instead. Given an estimation of the component values of the equivalent network with physics-based or empirical formulas for a microstrip patch antenna, the cost function to be optimized is close to convex near the initial guess. Moreover, the disparate sensitivities of the cost function with respect to optimization variables depends on the resonant frequency of the patch antenna and can be equalized by frequency scaling. The paper demonstrates how physics-based equivalent circuits can be automatically corrected to facilitate patch antenna design.

关键词： Equivalent circuits Microstrip antennas Patch antennas Resonance Cost function Impedance Feeds Network synthesis Resonant frequency Electronic design automation and methodology

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