The many cores design research community have shown high interest in optical crossbars on chip for more than a decade. Key properties of optical crossbars, namely a) contention-free data routing b) low-latency communi...
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ISBN:
(纸本)9781479977932
The many cores design research community have shown high interest in optical crossbars on chip for more than a decade. Key properties of optical crossbars, namely a) contention-free data routing b) low-latency communication and c) potential for high bandwidth through the use of WDM, motivate several implementations. These implementations demonstrate very different scalability and power efficiency ability depending on three key design factors: a) the network topology, b) the considered layout and c) the insertion losses induced by the fabrication process. The emerging design technique relying on multi-layer deposited silicon allows reducing optical losses, which may lead to significant reduction of the power consumption. In this paper, multi-layer deposited silicon based crossbars are proposed and compared. The results indicate that the proposed ring-based network exhibits, on average, 22% and 51.4% improvement for worst-case and average losses respectively compared to the most power-efficient related crossbars.
Integrated modular avionics architectures combined with the emerging SAE TTEthernet standard provides a strong infrastructure for the deployment of mixed-critical avionic applications having stringent safety, reliabil...
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Integrated modular avionics architectures combined with the emerging SAE TTEthernet standard provides a strong infrastructure for the deployment of mixed-critical avionic applications having stringent safety, reliability and performance requirements. The integration of such systems is a very complex and challenging engineering task. Therefore, a model-based approach, which endows system engineers with a methodology and the supporting tools to cope with this complexity, is of a paramount importance. In this research paper, we present an extension for the standard architecture and analysis modeling language AADL to enable modeling integrated multi-critical avionic applications deployed on TTEthernet-based IMA architectures. In particular, we present a metamodel which extends the core AADL metamodel with concepts and constraints relevant for this domain, we define the concrete textual syntax for this extension and we outline the implementation of this extension using the Open Source AADL Tool Environment (OSATE). Finally, we illustrate our AADL extension using a case study based on the Flight Management System.
The objective of this paper is to evaluate the applicability of different cavitation models and determine appropriate numerical parameters for cavitating flows around a hydrofoil. The simulations are performed for a N...
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The objective of this paper is to evaluate the applicability of mass transfer cavitation models and determine appropriate numerical parameters for cavitating flow simulations. CFD simulations were performed for a NACA...
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software performs a critical role in almost every aspect of our daily life specially in the embedded systems of medical equipments. A key goal of softwareengineering is to make it possible for developers to construct...
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One solution to handle large data sets is to organize and visualize them in a hierarchical model. This paper investigates hierarchical management of large trace logs and proposes an interactive zoomable timeline view ...
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One solution to handle large data sets is to organize and visualize them in a hierarchical model. This paper investigates hierarchical management of large trace logs and proposes an interactive zoomable timeline view to visualize the multiple levels of information generated by analyzing the execution trace logs. The view supports both the semantic (data) zooming and physical (visual) zooming. It displays a coarser layer first and provides some operations to explore and navigate the different layers of data. The method mainly facilitates the comprehension of the execution trace logs and can also be used to improve root cause analysis. The paper also discusses the hierarchical data model designed for organizing and visualizing the information at multiple levels.
The many-core design research community has shown high interest in optical crossbar on chip for more than a decade. Key properties of optical crossbars, namely (1) contention-free data routing, (2) low latency communi...
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In this paper, we address the problem of virtual machine (VM) placement in an InterCloud with regard to the reduction of carbon footprint in such computing environment. In order to minimize the data center Greenhouse ...
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In this paper, we address the problem of virtual machine (VM) placement in an InterCloud with regard to the reduction of carbon footprint in such computing environment. In order to minimize the data center Greenhouse Gas (GhG) emissions, this paper proposes a new mathematical formulation, where the placement approach is stated as a mixed integer programming problem which aims at minimizing the overall carbon footprint of the InterCloud. The proposed formulation presents an accurate carbon footprint evaluation based on joint optimization techniques, such as workload consolidation and cooling efficiency maximization, while considering the greenness of the data centers and the dynamic behavior of the IT equipment cooling fans. Simulation results showed that our model leads to optimal configurations with minimal carbon footprint in the InterCloud environment.
As computation schemes evolve and many new tools become available to programmers to enhance the performance of their applications, many programmers startedto look towards highly parallel platforms such as Graphical Pr...
As computation schemes evolve and many new tools become available to programmers to enhance the performance of their applications, many programmers started
to look towards highly parallel platforms such as Graphical Processing Unit (GPU). Offloading computations that can take advantage of the architecture of the GPU
is a technique that has proven fruitful in recent years. This technology enhances the speed and responsiveness of applications. Also, as a side effect, it reduces the
power requirements for those applications and therefore extends portable devices battery life and helps computing clusters to run more power efficiently.
Many performance analysis tools such as LTTng , strace and SystemTap already allow Central Processing Unit (CPU) tracing and help programmers to use CPU resources more efficiently. On the GPU side, different tools such as Nvidia ’s Nsight , AMD ’s CodeXL , and third party TAU and VampirTrace allow tracing Application Programming Interface (API) calls and OpenCL kernel execution. These tools are useful but are completely
separate, and none of them allow a unified CPU-GPU
tracing experience. We propose an extension to the existing scalable
and highly efficient LTTng tracing platform to allow
unified tracing of GPU along with CPU’s full tracing
capabilities.
Real-time systems have always been difficult to monitor and debug because of the timing constraints which rule out any tool significantly impacting the system latency and performance. Tracing is often the most reliabl...
Real-time systems have always been difficult to monitor and debug because of the timing constraints which rule out any tool significantly impacting the system latency and performance. Tracing is often the most reliable tool available for studying real-time systems. The real-time behavior of Linux systems has improved recently and it is possible to have latencies in the low microsecond range. Therefore, tracers must ensure that their overhead is within that range and predictable and scales well to multiple cores. The LTTng 2.0 tools have been optimized for multicore performance, scalability, and flexibility. We used and extended the real-time verification tool rteval to study the impact of LTTng on the maximum latency on hard real-time applications. We introduced a new real-time analysis tool to establish the baseline of real-time system performance and then to measure the impact added by tracing the kernel and userspace (UST) with LTTng . We then identified latency problems and accordingly modified LTTng-UST and the procedure to isolate the shielded real-time cores from the RCU interprocess synchronization routines. This work resulted in extended tools to measure the real-time properties of multicore Linux systems, a characterization of the impact of LTTng kernel and UST tracing tools, and improvements to LTTng .
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