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Evolvable hardware applied to nanotechnology

Evolvable hardware applied to nanotechnology

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1st NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2006

作者： Neto, Omar Paranaiba Vilela Pacheco, Marco Aurélio C. Masiero, Leone Pereira Barbosa, Carlos R. Hall Department of Electrical Engineering PUC-Rio Rio de Janeiro Brazil Post Graduation Program in Metrology PUC-Rio Rio de Janeiro Brazil

ISBN: (纸本)0769526144

This manuscript proposes the automatic design and synthesis of nanometer circuits and the optimization of molecular devices by the evolvable hardware technique. The potential of Evolvable Hardware is investigated by means of three different applications: synthesis of molecular electronic circuits, synthesis and optimization of Quantum-dot Cellular Automata (QCA) and the optimization of OLED (Organic Light-Emitting Diodes) parameters. The molecular electronic circuit synthesis is developed using the molecular transistor simulated in SPICE. QCA is a new paradigm used in the development of digital logical circuits, not using the flow of current. This new paradigm allows the development of a new generation of computers, faster and with smaller energy dissipation. Finally, the optimization of OLED parameters is developed using the electrical behavior model of a multi-layer device. In this model, each sub-layer in the emissive layer has a ratio of ETM (Electron Transport Material) and a ratio of HTM (Hole Transport Material). The first results show that the technique is able to synthesize and optimize circuits that perform the logic specified by the user, avoiding noise and other problems that could lead to malfunction. Moreover, the EHW technique is able to optimize the parameters of an organic device, such as OLED. © 2006 IEEE.

关键词： Computer hardware

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Evolvable Hardware Applied to Nanotechnology

Evolvable Hardware Applied to Nanotechnology

引用

NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

作者： O.P. Vilela Neto L. Pereira Masiero M.A. C. Pacheco C.R. Hall Barbosa Department of Electrical Engineering PUC-Rio Rio de Janeiro Brazil Post Graduation Program in Metrology PUC-Rio Rio de Janeiro Brazil

This manuscript proposes the automatic design and synthesis of nanometer circuits and the optimization of molecular devices by the evolvable hardware technique. The potential of evolvable hardware is investigated by means of three different applications: synthesis of molecular electronic circuits, synthesis and optimization of quantum-dot cellular automata (QCA) and the optimization of OLED (organic light-emitting diodes) parameters. The molecular electronic circuit synthesis is developed using the molecular transistor simulated in SPICE. QCA is a new paradigm used in the development of digital logical circuits, not using the flow of current. This new paradigm allows the development of a new generation of computers, faster and with smaller energy dissipation. Finally, the optimization of OLED parameters is developed using the electrical behavior model of a multi-layer device. In this model, each sub-layer in the emissive layer has a ratio of ETM (electron transport material) and a ratio of HTM (hole transport material). The first results show that the technique is able to synthesize and optimize circuits that perform the logic specified by the user, avoiding noise and other problems that could lead to malfunction. Moreover, the EHW technique is able to optimize the parameters of an organic device, such as OLED

关键词： Hardware Nanotechnology Circuit synthesis Organic light emitting diodes Quantum cellular automata Molecular electronics Nanoscale devices Design optimization Quantum dots Computational modeling

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Preliminary comparison of different neural-fuzzy mappers for load curve short term prediction

Preliminary comparison of different neural-fuzzy mappers for...

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Seminar on Neural Network Applications in electrical engineering

作者： Dzenana Malkocevic Tatjana Konjic Vladimiro Miranda TEMPUS CEFES post-graduation program Universities of Tuzla (BiH) Novi Sad Serbia Faculty of Electrical Engineering University of Tuzla Bosnia and Herzegovina INESC Porto research institute University of Porta Portugal

This paper is written with the didactic purpose of exploring and indicating possibilities to power companies in the Balkan region for the application of adaptive neuro-fuzzy inference system (ANFIS) models in load prediction with real load data set. ANFIS models were trained and tested using 15-minute load data collected in Portugal by the electric power company EDP during a 42 day period. Simulation results gave promising results especially considering small size of used data set. Although the objective of the paper is to demonstrate possibilities for practical implementation, further research and improvement including the contributions of similar approaches in the world must be done

关键词： Power system modeling Load forecasting Power system dynamics Adaptive systems Predictive models Power system control Power system planning Neural networks Fuzzy systems Power systems

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Reconfigurable Gang Scheduling Algorithm

Reconfigurable Gang Scheduling Algorithm

引用

10th International Workshop on Job Scheduling Strategies for Parallel Processing, JSSPP 2004

作者： Góes, Luís Fabrício Wanderley Da Silva Martins, Carlos Augusto Paiva Pontifical Catholic University of Minas Gerais Post-Graduation Program in Electrical Engineering Av. Dom José Gaspar 500 Belo Horizonte Minas Gerais Brazil

Using a single traditional gang scheduling algorithm cannot provide the best performance for all workloads and parallel architectures. A solution for this problem is an algorithm that is capable of dynamically changing its form (configuration) into a more appropriate one, according to environment variations and user requirements. In this paper, we propose, implement and analyze the performance of a Reconfigurable Gang Scheduling Algorithm (RGSA) using simulation. A RGSA uses combinations of independent features that are often implemented in GSAs such as: packing and re-packing schemes (alternative scheduling etc.), multiprogramming levels etc. Ideally, the algorithm may assume infinite configurations and it reconfigures itself according to entry parameters such as: performance metrics (mean utilization, mean response time of jobs etc.) and workload characteristics (mean execution time of jobs, mean parallelism degree of jobs etc.). Also ideally, a reconfiguration causes the algorithm to output the best configuration for a particular situation considering the system's state at a given moment. The main contributions of this paper are: the definition, proposal, implementation and performance analysis of RGSA. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Parallel processing systems

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Development of a low intensity magnetic field transducer for biomedical application based on the Giant Magnetoimpedance effect

Development of a low intensity magnetic field transducer for...

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International Measurement Federation, IMEKO - Symposium on Metrology and Measurement Applications in the Era of Internet Working 2005

作者： Pompéia, Flávia Gusmão, Luiz A.P. Barbosa, Carlos H. Monteiro, Elisabeth C. Gonsalves, Lídice A.P. MacHado, Fernando L.A. Post Graduation Program in Metrology Pontifícia Universidade Católica Do Rio de Janeiro PUC-Rio 22453-900 Rio de Janeiro Brazil Department of Electrical Engineering PUC-Rio Rio de Janeiro Brazil Department of Physics UFPE Recife Brazil Department of Material Engineering Universidade Federal de Pernambuco UFPE Recife Brazil

ISBN: (纸本)9781622766970

This manuscript presents the development of a low intensity magnetic field transducer, based on the Giant Magnetoimpedance (GMI) effect, to be used for biomedical applications. The GMI effect is a characteristic of some ferromagnetic materials, due to which it is observed a large variation of the material impedance due to external dc magnetic fields. We describe the effect, the transducer configuration, the electronic circuits and the preliminary results obtained so far. A sensitivity comparable to a fluxgate probe has already been obtained, and the theoretical calculations indicate the possibility of further enhancing this figure of merit.

关键词： Ferromagnetic materials

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RJSSim: A reconfigurable job scheduling simulator for parallel processing learning 33

RJSSim: A reconfigurable job scheduling simulator for parall...

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33rd Annual Frontiers in Education, FIE 2003

作者： Góes, Luís F.W. Martins, Carlos A.P.S. Pontifical Catholic University of Minas Gerais Post-Graduation Program in Electrical Engineering Computational and Digital Systems Laboratory Belo HorizonteMG Brazil Pontifical Catholic University of Minas Gerais Computer Science Department Post-Graduation Program in Electrical Engineering Computational and Digital Systems Laboratory Belo HorizonteMG Brazil

ISBN: (纸本)0780379616

In this work, we present and analyze the use of a reconfigurable job scheduling simulator called RJSSim as an aid tool for parallel processing learning. This software is a functional and performance Java-based simulator of job scheduling policies. Our objectives are: to present RJSSim;to show the use of RJSSim and reconfigurability concepts for parallel processing learning. First, we present a prototype of RJSSim and the reconfigurability concept. Then we describe two case studies remarking the main parallel processing concepts and skills students can learn. In the first case study, we analyze two parallel algorithm models. In the second, we do some performance tests among parallel (reconfigurable) scheduling policies and architectures. Then, we analyze the performance through some metrics like response time, idle time etc. Finally we discuss and analyze the use of RJSSim for parallel processing learning. Our main contribution is: an implementation of RJSSim for parallel processing learning. © 2003 IEEE.

关键词： Parallel algorithms

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Performance analysis of parallel programs using prober as a single aid tool 14

Performance analysis of parallel programs using prober as a ...

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14th Symposium on Computer Architecture and High Performance Computing

作者： Góes, LFW Ramos, LES Martins, CAPS Informatics Institute Post-Graduation Program in Electrical Engineering Pontifical Catholic University of Minas Gerais Brazil

ISBN: (纸本)0769517722

Prober is a functional and performance analysis tool for parallel programs, developed during an undergraduate research project. In this paper we show the new expanded version of Prober, in which some features from different software tools are aggregated. It can be used as a single tool to aid the developer in the performance analysis of parallel programs. Our main goal is to provide a new version of Prober, with additional features. Among them we can highlight: the interpretation of user scripts, a user-level support library the generation of speedup and efficiency graphics, batch execution and a new user interface. In order to show, verify and analyze the use of the new version of Prober, we did performance tests in a parallel image convolution program. We added performance measuring routines to collect performance data within different internal code segments;built a set of scripts to specify the performance tests;ran the set of scripts in batch mode;used Prober to generate graphics and statistics based on the collected performance data;and analyzed the results rising Prober as an aid tool.

关键词： Convolution Graphics Image analysis Image segmentation Performance analysis Radio access networks Software libraries Software tools Testing User interfaces

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Performance analysis of parallel programs using Prober as a single aid tool

Performance analysis of parallel programs using Prober as a ...

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International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)

作者： L.F.W. Goes L.E.S. Ramos C.A.P.S. Martins Informatics Institute Post-Graduation Program in Electrical Engineering Pontifical Catholic University of Minas Gerais Brazil

Prober is a functional and performance analysis tool for parallel programs, developed during an undergraduate research project. In this paper we show the new expanded version of Prober, in which some features from different software tools are aggregated. It can be used as a single tool to aid the developer in the performance analysis of parallel programs. Our main goal is to provide a new version of Prober, with additional features. Among them we can highlight: the interpretation of user scripts, a user-level support library, the generation of speedup and efficiency graphics, batch execution and a new user interface. In order to show, verify and analyze the use of the new version of Prober, we did performance tests in a parallel image convolution program. We added performance measuring routines to collect performance data within different internal code segments; built a set of scripts to specify the performance tests; ran the set of scripts in batch mode; used Prober to generate graphics and statistics based on the collected performance data; and analyzed the results using Prober as an aid tool.

关键词： Performance analysis Graphics Testing Software tools Software libraries User interfaces Image analysis Convolution Image segmentation Radio access networks

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Simulation tool of network processor for learning activities

Simulation tool of network processor for learning activities

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Frontiers in Education (FIE) Conference

作者： H.C. de Freitas C.A.P. da Silva Martins Post-Graduation Program in Electrical Engineering Student Pontifical Catholic University of Minas Gerais Belo Horizonte Minas Gerais Brazil Post-Graduation Program in Electrical Engineering Professor Pontifical Catholic University of Minas Gerais Belo Horizonte Minas Gerais Brazil

We present a functional simulation tool of the network processor developed at the Pontifical Catholic University of Minas Gerais, Brazil. It started during an undergraduate research project. The instruction set and microarchitecture of this type of processor are specialized and dedicated to work in network layers. Our main goals are improving and optimizing the learning activities related to the network processor for engineering and computer science users.

关键词： Microarchitecture Computer networks Computer aided instruction Logic Buffer storage Read-write memory Computer architecture Registers Switches Reduced instruction set computing

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A new learning method of microprocessor architecture

A new learning method of microprocessor architecture

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Frontiers in Education (FIE) Conference

作者： C.A.P.S. Martins J.B.T. Correa L.F.W. Goes L.E.S. Ramos T.H. Medeiros Prof Informatics Institute and Post-Graduation Program in Electrical Engineering Pontifical Catholic University of Minas Gerais Belo Horizonte Minas Gerais Brazil Pontificia Universidade Catolica de Minas Gerais Belo Horizonte MG BR

We present a new learning method of microprocessor architecture based on design and verification using functional simulation. Our main goals are to improve and optimize the learning process, motivating students to study and learn theoretical and practical aspects of microprocessor architecture, using functional simulators to validate the microprocessor design and to construct knowledge; and develop research activities during an undergraduate course. Our method is based on learning, constructivism theory, problem based learning, group projects, design of academic microprocessors as motivation for theory study/learning and verification of designed microprocessors through functional simulators developed by students. To validate the proposed method we analyze two microprocessors and functional simulators: a digital signal processor using ASIP and RISC concepts, and a RISC ASIP home automation processor. They were developed in a computer architecture course (computer science, PUC-Minas, Brazil) as the application of this method. In the conclusion students and professor analyze the results, highlighting the main differences, advantages and disadvantages of the new method.

关键词： Learning systems Microprocessors Computational modeling Application specific processors Reduced instruction set computing Design optimization Signal analysis Analytical models Digital signal processors Home automation

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