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Fast Chaotic Image Encryption with Simultaneous Permutation and Diffusion for IoT Applications

Fast Chaotic Image Encryption with Simultaneous Permutation ...

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GLOBECOM 2022 - 2022 IEEE Global Communications Conference

作者： João Inácio Moreira Bezerra Gustavo Machado Rafael Soares Alexandre Molter Vinícius V. Camargo Postgraduate Program in Computing - PPGC Postgraduate Program in Mathematical Modeling Federal University of Pelotas - UFPel Pelotas Brazil

ISBN: (纸本)9781665435413

The current prevalence of the internet for secret communication, alongside the development of the Internet of Things (IoT), increases the importance of cryptography for information security. Considering that the most widely shared archives are images and that traditional encryption algorithms, such as the Advanced Encryption Standard (AES), are not optimized for image encryption, researchers have investigated the use of chaos theory in image encryption schemes. However, their elevated encryption time and memory access, due to the number of scannings needed to cipher an image, have been an issue for chaotic ciphers. Considering this, a new cipher is proposed in this work in which the plain-image is divided into blocks and a simultaneous permutation-diffusion is adopted, increasing the cipher's time efficiency. The cipher is executed in a Raspberry Pi 3 device, and it presents a significant increase in throughput compared to other similar works in literature. Additionally, extensive security evaluations showed that the cipher is secure relative to statistical, differential, chosen-plaintext, brute force, noise, and occlusion attacks, which are hence suitable for the application in real-time IoT applications.

关键词： Ciphers Runtime Chaotic communication Memory management Throughput Real-time systems Encryption

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Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design

Calibration of Logical Effort Transistor Sizing for On-the-F...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Henrique Kessler Murilo Bohlke Leomar S. da Rosa Marcelo Porto Viní cius V. Camargo Postgraduate Program in Computing - PPGC Federal University of Pelotas - UFPel Pelotas Brazil Center for Technological Development - CDTec*

Gate sizing has been widely studied to improve power dissipation and performance characteristics in VLSI design. Recent developments allow the automatic design of static CMOS complex gates for a reduction in power dissipation. It is possible to observe a lack of different transistor sizing in these works using minimum transistor dimension or the Logical Effort technique. In this work, we propose a methodology to adapt the Logical Effort technique for low-power applications. Results show significant improvements on up to 99.9% of the studied cases in power-performance trade-off across multiple simulation environments for a 45nm CMOS technology.

关键词： Semiconductor device modeling Circuits and systems Logic gates Very large scale integration Benchmark testing CMOS technology Libraries

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Low Complexity Broadband Array Processing in Dynamic Scenarios with Jamming

Low Complexity Broadband Array Processing in Dynamic Scenari...

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IEEE Conference on Vehicular Technology (VTC)

作者： Daniel V. De Lima João Paulo J. Da Costa Ricardo K. Miranda Antonio Arlis S. Da Silva Giovanni A. Santos José Alfredo R. Vargas Auzuir R. De Alexandria Postgraduate Program in Telecommunications Engineering (PPGET) IFCE Fortaleza Brazil Hamm-Lippstadt University of Applied Sciences (HSHL) Lippstadt Germany Graduate School for Applied Research in North Rhine-Westphalia (PKNRW) Bochum Germany Karlsruhe Institute of Technology (KIT) Karlsruhe Germany Graduate Program in Computing (PPGC) UFRGS Porto Alegre Brazil Postgraduate Program in Mechatronics Engineering (PPMEC) UnB Brasilia Brazil

ISBN: (数字)9798350387414

ISBN: (纸本)9798350387421

Vehicle-to-Everything (V2X) networks require low-latency communications utilizing a broad spectrum while operating under jamming. In this sense, low complexity antenna array-based broadband jamming mitigation schemes are crucial in order to allow low latency communication and low-cost hardware. In this paper we propose low-complexity algorithms for signal recovery in broadband processing scenario applied to V2X. Numerical simulation of a jamming scenario demonstrate the proposed algorithm achieving the same performance in terms of signal-to-interference plus noise ratio (SINR) as the state-of-the-art while taking signiflcantly less time to compute.

关键词： Heuristic algorithms Prevention and mitigation Interference Numerical simulation Broadband communication Broadband antennas Jamming

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Efficient hardware design for the AV1 CDEF filter targeting 4K UHD videos 52

Efficient hardware design for the AV1 CDEF filter targeting ...

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52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020

作者： Zummach, Eduardo Palau, Roberta Palomino, Jones Goebel Daniel Agostini, Luciano Porto, Marcelo Postgraduate Program in Computing PPGC Video Technology Research Group ViTech Federal University of Pelotas UFPEL Brazil

ISBN: (纸本)9781728133201

Developed by the AOMedia industry consortium, the AOM Video 1 (AV1) is an open-source and royalty-free video encoder released in June 2018. The Constrained Directional Enhancement Filter (CDEF) is one of the three AV1 in-loop filters and it is the focus of this work. The CDEF has the goal to reduce ringing artifacts generated with the encoding process, acting as a directional deringing filter. This paper presents a hardware design for the AV1 CDEF targeting real-time processing of 4K Ultra High Definition (UHD) videos. The architecture was synthesized to ASIC using the 40nm TSMC library, requiring 185 kgates and with a power dissipation of 43 mW when running at 93 MHz, reaching the frame rate of 60 frames per second (fps). To the best of the author's knowledge, there is no other work in the literature with dedicated hardware design for the AV1 CDEF. © 2020 IEEE

关键词： Video signal processing

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High-Throughput CDEF Architecture for the AV1 Decoder Targeting 4K@60fps Videos

High-Throughput CDEF Architecture for the AV1 Decoder Target...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Eduardo Zummach Roberta Palau Jones Goebel Luciano Agostini Marcelo Porto Postgraduate Program in Computing – PPGC

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

This paper presents a high throughput architecture for the Constrained Directional Enhancement Filter (CDEF) defined in the AOM Video 1 (AV1) decoder. CDEF is one of the three in-loop filters of the AV1 that, together, aim to reduce different types of coding artifacts. The CDEF is used as a deringing filter in this context. The proposed CDEF hardware architecture implements its both operations: The Direction Search module and the Non-Linear Low Pass Filter, processing 64 luminance or 16 chrominance samples per clock cycle. This architecture can process Ultra-High Definition (UHD) videos at 60 frames per second when running at only 23 MHz. The architecture was synthesized to ASIC using the 40nm TSMC library, requiring 369K gates and with a power dissipation of 65 mW. At the best of the authors' knowledge, this is the first hardware design targeting the AV1 CDEF filter presented in the literature.

关键词： Videos Computer architecture Damping Hardware Kernel Decoding Low pass filters

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Broadband Beamforming via Frequency Invariance Transformation and PARAFAC Decomposition for Jamming Mitigation in V2X Scenarios

Broadband Beamforming via Frequency Invariance Transformatio...

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IEEE Conference on Vehicular Technology (VTC)

作者： Daniel V. de Lima João Paulo J. da Costa Antonio Arlis S. da Silva Giovanni A. Santos José Alfredo R. Vargas Auzuir R. de Alexandria Postgraduate Program in Telecommunications Engineering (PPGET) IFCE Fortaleza Brazil Hamm-Lippstadt University of Applied Sciences (HSHL) Lippstadt Germany Graduate School for Applied Research in North Rhine-Westphalia (PKNRW) Bochum Germany Karlsruhe Institute of Technology (KIT) Karlsruhe Gennany Graduate Program in Computing (PPGC) UFRGS Porto Alegre Brazil Department of Electrical Engineering UnB Brasilia Brazil

ISBN: (数字)9798350387414

ISBN: (纸本)9798350387421

Vehicle-to-Everything (V2X) communication can considerably improve the efficiency and safety of autonomous driving and advanced driver-assistance systems (ADASs). However, V2X communication can be considerably degraded in the presence of cyberattacks, such as radio jamming. Traditionally, beamforming techniques can be applied to increase the signal-to-interference plus noise ratio (SINR). This paper evaluates broadband beamforming in the mmWave spectrum against radio jamming in V2X communication. The exploitation of the mm Wave spectrum in 5G-V2X communication has a natural advantage against radio jamming. First, attenuation is stronger in the mmWave spectrum in the range of 40 GHz or higher than in the traditional 5.9 GHz. Second, to generate broadband radio jamming, the radio jammer requires much more complex hardware and energy consumption. Third, by using broadband beamforming, broadband radio jamming can be considerably attenuated, limiting the degradation of the spectrum by the radio jamming. According to our numerical results, gains of close to 30 dB SINR can be achieved. We propose a broad-band beamforming technique based on the canonical polyadic decomposition via generalized eigenvalue decomposition (CPD-GEVD). The CPD-GEVD broadband beamforming outperforms state-of-the-art beamforming algorithms in most V2X scenarios presented in this paper.

关键词： Vehicular and wireless technologies Array signal processing Interference Attenuation Broadband communication Jamming Millimeter wave communication

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Efficient Hardware Design for the AV1 CDEF Filter Targeting 4K UHD Videos

Efficient Hardware Design for the AV1 CDEF Filter Targeting ...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Eduardo Zummach Roberta Palau Jones Goebel Daniel Palomino Luciano Agostini Marcelo Porto Postgraduate Program in Computing - PPGC Video Technology Research Group - ViTech Federal University of Pelotas - UFPEL Brazil

ISBN: (数字)9781728133201

ISBN: (纸本)9781728133218

关键词： Videos Hardware FCC Decoding Damping Industries Encoding

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A New Method Based on Deep Learning to Detect Lesions in Retinal Images using YOLOv5

A New Method Based on Deep Learning to Detect Lesions in Ret...

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IEEE International Conference on Bioinformatics and Biomedicine (BIBM)

作者： Carlos Santos Marilton Aguiar Daniel Welfer Bruno Belloni Federal Institute of Education Science and Technology Farroupilha Alegrete Brazil Postgraduate Program in Computing (PPGC) Federal University of Pelotas Pelotas Brazil Departament of Applied Computing Federal University of Santa Maria Santa Maria Brazil Federal Institute of Education Science and Technology Sul-Rio-Grandense Passo Fundo Brazil

ISBN: (纸本)9781665429825

Diabetic Retinopathy is one of the leading causes of vision loss and presents in its initial phase retinal lesions, such as microaneurysms, hemorrhages, and hard and soft exudates. Therefore, computational models capable of detecting these lesions can help in the early diagnosis of the disease and prevent the manifestation of more severe forms of lesions, helping define the best form of treatment. This work proposes a method based on deep neural network models that perform one-stage object detection, using state-of-the-art data augmentation and transfer learning techniques to present a model that aids in the medical diagnosis of fundus lesions. The model was trained, adjusted, and evaluated using the DDR Diabetic Retinopathy Dataset, and implemented based on the YOLOv5 architecture and the PyTorch framework, achieving values for mAP of 0.1040 and 0.0283 for IoU threshold of 0.5 and 0.5:0.95 respectively, in the validation set. The results obtained in the experiments demonstrate that the proposed method presented superior results to equivalent works found in the literature.

关键词： Deep learning Training Retinopathy Neural networks Computer architecture Retina Data models

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A Low-Complexity Algorithm and Its Low-Power and High-Throughput Architecture for 3D-HEVC DMM-1 Encoding Tool

A Low-Complexity Algorithm and Its Low-Power and High-Throug...

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IEEE Latin American Symposium on Circuits and Systems (LASCAS)

作者： Vinicius Borges Murilo Perleberg Vladimir Afonso Marcelo Porto Luciano Agostini Video Technology Research Group (ViTech) Federal University of Pelotas (UFPEL) Pelotas RS Brazil Postgraduate Program in Computing (PPGC) Video Technology Research Group (ViTech) Federal University of Pelotas (UFPEL) Pelotas RS Brazil Sul-rio-grandense Federal Institute (IFSul) Pelotas RS Brazil

ISBN: (数字)9781728134277

ISBN: (纸本)9781728134284

This paper presents a low-power and high-performance hardware design for the Depth Modeling Mode 1 (DMM-1) of the 3D-High Efficiency Video Coding (3D-HEVC). The designed architecture is based on a low-complexity algorithm developed to reduce the DMM-1 computational effort and to avoid the use of memory. The architecture was described in VHDL, and the ASIC synthesis was performed for the TSMC 40nm technology. The synthesis results showed a gate count of 1,283k gates and a power dissipation of 51.36 mW, when running at 82 MHz. The designed architecture is capable of processing 3D 1080p videos with up to 11 views at 30 frames per second. The reached results surpass the published works in terms of throughput and power dissipation.

关键词： Encoding Computer architecture Hardware Calculators Tools Video coding Three-dimensional displays

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Hybrid Memory Cube in Embedded Systems

Hybrid Memory Cube in Embedded Systems

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Symposium on Integrated Circuits and Systems Design (SBCCI)

作者： Carlos Michel Betemps Mauricio Lima Pilla Bruno Zatt Federal University of Pampa (UNIPAMPA) Bagé RS Brazil Postgraduate Program in Computing (PPGC) Federal University of Pelotas (UFPel) Pelotas RS Brazil

ISBN: (纸本)9781538674321

This paper presents an evaluation of the Hybrid Memory Cube (HMC) usage in the Embedded Systems (ES) context. HMC can provide less use of energy and physical area - primary design goals for ES - and despite satisfying tight performance requirements. Our experiments' settings have used modest configurations of L1 and L2 caches in conjunction with the main memory of LPDDR3 or HMC types. gem5 was used to simulate four MiBench applications in a 4-CPU architecture. Estimations about time, energy, and area were made using CasHMC, CACTI, and a power calculator. The HMC memory allows improvements in execution time and consumed energy. In some situations, this memory type permits removing the L2 cache from the memory hierarchy. EDP (Energy Delay Product) and EDAP (Energy-Delay Area Product) metrics show that HMC provides both energy efficiency and improved density when compared to LPDDR3. In average, EDP and EDAP values for HMC settings were nearly 85% and 92% lower than LPDDR3 ones, respectively.

关键词： Estimation Embedded systems Energy consumption Tools Calculators Bandwidth Random access memory

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