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Failure analysis system for submicron semiconductor devices

Hitachi Review 2006年第2期55卷 68-72页

作者： Fukui, Munetoshi Mitsui, Yasuhiro Nara, Yasuhiko Yano, Fumiko Furukawa, Takashi Application Technology Department Advanced Equipment and Systems Sales Division Hitachi High-Technologies Corporation Advanced Microscope Systems Design Department Nanotechnology Products Business Group Hitachi High-Technologies Corporation Failure Analysis Technology Group Process and Device Analysis Engineering Development Department Renesas Technology Corp. Advanced Technology Research Department Central Research Laboratory

Failure analysis of semiconductor device is becoming increasingly difficult as VLSI technology evolves toward smaller features and semiconductor device structures become more complex. Especially considering that the defective area obtained through diagnosis pin-pointing faulty sites is not the same size as the area subjected to physical analysis, and this disparity becomes more pronounced as feature sizes shrink. This prompted us to develop an extremely fine scaled SEM mechanical probing system permitting identification of minute fault sites. The development involved a number of related projects including investigation of a precision probe and stage mechanism that can deal with submicron semiconductor devices, a six-probe mechanism for expanded capabilities of performing inverter measurements and precision single transistor measurements, a probe and sample exchange mechanism that works while under vacuum to achieve high throughput, and a robust CAD navigation system. The system is now ready and available for practical application to 65-nm feature devices, and can be readily adapted to at least the next couple of generation nodes.

关键词： Failure analysis

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Identification of electromigration dominant diffusion path for Cu damascene interconnects and effect of plasma treatment and barrier dielectrics on electromigration performance 42

Identification of electromigration dominant diffusion path f...

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42nd Annual IEEE International Reliability Physics Symposium, IRPS 2004

作者： Usui, T. Oki, T. Miyajima, H. Tabuchi, K. Watanabe, K. Hasegawa, T. Shibata, H. SoC Research and Development Center Semiconductor Company Toshiba Corporation 8 Shinsugita-cho Isogo-ku Yokohama235-8533 Japan Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation 8 Shinsugita-cho Isogo-ku Yokohama235-8533 Japan Semiconductor Technology Development Division Micro Systems Network Company Sony Corporation Japan

ISBN: (纸本)078038315X

Electromigration testing pattern to identify the dominant diffusion path of Copper (Cu) damascene interconnects is proposed. It is confirmed that dominant diffusion path is the interface between Cu and barrier dielectrics using the proposed testing pattern. After identification of the dominant path, the effects of the plasma treatment and barrier dielectric SiCxNy and SiCx on the EM performance is investigated. Failure analysis reveals that Cu oxide at the interface of SiCx samples with H2 plasma treatment accelerates the Cu EM diffusion, resulting in lower activation energy and shorter lifetime. In addition, it is also found that nitrogen at the interface retards Cu diffusion drastically. © 2004 IEEE.

关键词： Electromigration

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Adsorption and Self‐Assembly of Peptides on Mica Substrates†

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Angewandte Chemie 2005年第13期117卷

作者： Conor Whitehouse Jiyu Fang Amalia Aggeli Mark Bell Rik Brydson Colin W. G. Fishwick Jim R. Henderson Charles M. Knobler Robert W. Owens Neil H. Thomson D. Alastair Smith Neville Boden Centre for Self‐Organising Molecular Systems Department of Chemistry University of Leeds Leeds LS2 9JT UK Fax: (+44) 113‐343‐6452 Present address: Research and Development Division Fujirebio Inc. 51 Komiya‐cho Hachioji‐shi Tokyo 192‐0031 Japan Fax: (+81) 426‐468‐325 Department of Chemistry and Biochemistry University of California Los Angeles CA 90095‐1569 USA Institute for Materials Research School of Process Environmental and Materials Engineering University of Leeds Leeds LS2 9JT UK Department of Physics and Astronomy University of Leeds Leeds LS2 9JT UK

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Flash lamp annealing technology for ultra-shallow junction formation 3

Flash lamp annealing technology for ultra-shallow junction f...

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3rd International Workshop on Junction Technology, IWJT 2002

作者： Ito, T. Suguro, K. Tamura, M. Taniguchi, T. Ushiku, Y. Iinuma, T. Itani, T. Yoshioka, M. Owada, T. Imaoka, Y. Murayama, H. Kusuda, T. Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation 8 Shinsugita-cho Isogo-ku Yokohama Japan TCI Division Toshiba I.S. Corporation Japan Information Systems Center Toshiba Corporation Japan Lamp Technology and Engineering Division Ushio Inc. Japan Development Department for Electronics Equipment Dainippon Screen Mfg. Co. Ltd. Japan

ISBN: (纸本)4891140283

As a new method of activating implanted impurities, flash lamp annealing (FLA) technology is proposed. By optimizing FLA and implantation conditions, junction depth of 14 nm and the sheet resistance of 770 Ω/sq. with good junction leakage were successfully obtained for p+/n junctions without wafer slip and warpage problems. © 2002 JSAP.

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Flash lamp annealing technology for ultra-shallow junction formation

Flash lamp annealing technology for ultra-shallow junction f...

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International Workshop on Junction Technology

作者： T. Ito K. Suguro M. Tamura T. Taniguchi Y. Ushiku T. Iinuma T. Itani M. Yoshioka T. Owada Y. Imaoka H. Murayama T. Kusuda Process and Manufacturing Engineering Center Toshiba Corporation Isogo-ku Yokohama Japan Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Yokohama Japan TCI Division Toshiba I.S Corporation Information Systems Center Toshiba Corporation Japan Lamp Technology and Engineering Division Ushio Inc. Development Department for Electronics Equipment Dainippon Screen MFG. Co. Ltd. Development Department for Electronics Equipment Dainippon Screen MFG. Co. Ltd. Yokohama Japan

ISBN: (纸本)4891140283

As a new method of activating implanted impurities, flash lamp annealing (FLA) technology is proposed. By optimizing FLA and implantation conditions, junction depth of 14 nm and the sheet resistance of 770 /spl Omega//sq. with good junction leakage were successfully obtained for p/sup +//n junctions without wafer slip and warpage problems.

关键词： Lamps Temperature Heating Rapid thermal annealing MOSFETs Electrical resistance measurement Indium tin oxide Manufacturing processes Electronic equipment manufacture Semiconductor device manufacture

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In-line wafer inspection data warehouse for automated defect limited yield analysis

In-line wafer inspection data warehouse for automated defect...

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IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing

作者： H. Iwata M. Ono J. Konishi S. Isogai T. Furutani Integrated Manufacturing Process Department Production Engineering Research Laboratory Hitachi and Limited Yokohama Japan Electronics Systems Cluster Instruments Hitachi and Limited Hitachinaka Ibaraki Japan Development Division Hitachi VIdeo and Information Systems Inc. Yokohama Japan

ISBN: (纸本)0780359216

A data warehouse approach for the automation of process zone-by-zone defect limited yield analysis is presented in this paper. The system employs pre-calculation of adder defects extraction and clustered defects recognition, a newly developed wafer-wise defect record structure, and a graphical user interface purpose-designed for data selection navigation. Analysis time can be reduced to less than 1% of that of benchmarked conventional procedures.

关键词： Inspection Data warehouses Integrated circuit yield Manufacturing processes Data analysis Circuit faults Optical microscopy Production engineering Laboratories Instruments

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Combination of TCAD and physical MOSFET model for LSI development time reduction

Combination of TCAD and physical MOSFET model for LSI develo...

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IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing

作者： K. Ishimaru K. Kasai Y. Fukaura Y. Okayama T. Imamura S. Irie T. Hirano K. Watanabe M. Ueno K. Hashimoto F. Matsuoka Memory LSI Research and Development Center Yokohama Japan Memory Division Yokohama Japan Toshiba Microelectronics Corporation Yokohama Japan System LSI Division Yokohama Japan Toshiba CAE Systems Inc. Yokohama Japan Process Engineering Center Semiconductor Company Toshiba Corporation Yokohama Japan

Advantage of MOSFET SPICE parameter prediction by combining TCAD and BSIM3 model is presented. This method can release sufficient SPICE parameters without wafer fabrication. Lithography TCAD can reduce pattern optimiz... 详细信息

ISBN: (纸本)0780359216

关键词： MOSFET circuits Large scale integration SPICE Fabrication Semiconductor device modeling Predictive models Circuit synthesis Lithography Random access memory Time to market

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Cesium sorption behavior of a mordenite type synthetic zeolite and its modified form obtained by acid treatment

Cesium sorption behavior of a mordenite type synthetic zeoli...

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作者： Samanta, S.K. Process Engineering and Systems Development Division Bhabha Atomic Research Centre Trombay Mumbai 400 085 India

A locally produced mordenite type synthetic zeolite and its modified form obtained by the treatment with dilute hydrochloric acid were tested for their cesium uptake characteristics. The two zeolites were compared with other commercially available synthetic zeolites with respect to their ability to sorb radiocesium from dilute nitric acid solution. The effects of the changes in the composition of the solution including the concentration of nitric acid, sodium and cesium on the uptake of cesium were investigated. The results can be used in the removing processor radiocesium from different types of nuclear plant effluents by these zeolites.

关键词： Zeolites

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A novel method for resist removal after etching of the organic SOG layer with the use of adhesive tape

A novel method for resist removal after etching of the organ...

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IEEE International Symposium on Semiconductor Manufacturing

作者： Y. Terada E. Toyoda M. Namikawa A. Maekawa T. Tokunaga Semiconductor Material Division Nitto Denko Corporation Nakahara Aichi Japan Makoto Namikawa Semiconductor Material Division Nitto Denko Corporation Toyohashi Aichi Japan Process Engineering Development Department ULSI Development Operation Hitachi ULSI Systems Company Limited Omeshi Tokyo Japan Process Development Department Device Development Center. Hitachi and Limited Omeshi Tokyo Japan

A novel methods for resist removal, which is applicable to Cu wiring fabrication, is described here. With the use of a well-designed adhesive tape, the resist can be removed from the silicon wafer very easily, after the dry etching process of the interlayer dielectric consisting of an organic spin-on-glass (SOG) layer. Organic contamination of the wafer is comparatively satisfactory, and there is no organic material residue from the adhesive tape. Furthermore, the characteristic of this removal process, using adhesive tape, causes no oxidation damage to the organic SOG layer observed by using the conventional O/sub 2/ plasma ashing method. The adhesive tape process is fairly useful in fabrication, using organic low-dielectric-constant (low-k) materials such as the organic SOG layer, and seems to be applicable to other resist removing processes in which the plasma ashing application would not be used.

关键词： Resists Fabrication Organic materials Plasma applications Plasma materials processing Wiring Silicon Dry etching Dielectrics Contamination

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Sorption of radioactive strontium on a silica-titania mixed hydrous oxide gel

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JOURNAL OF RADIOANALYTICAL AND NUCLEAR CHEMISTRY 1997年第1期220卷 55-58页

作者： Venkatesan, KA Sasidharan, NS Wattal, PK Process Engineering and Systems Development Division Bhabha Atomic Research Centre Mumbai India

A silica-titania (Si-Ti) mixed hydroxide gel with Ti to Si mole ratio of 1 : 1 was prepared Studies on the sorption of radiostrontium from alkaline solutions having various concentrations of sodium were carried out with Si-Ti. The distribution coefficient (K-d) of strontium decreased with increasing concentrations of sodium from 0.1 to 4.0 ***(-3). The plot of log K-d versus log [Na+] gave a slope of -0.55 as against the theoretical value of -2.0. This suggests that some other paths in addition to the simple stoichiometric ion exchange is also existing for sorption. From pH titrations the pH(pzc) of Si-Ti was found to be 4.22 coinciding nearly with the pH sorption edge. An attempt was made to correlate the sorption results with the surface characteristics of the sort,ent. It was found that sorption is favored when the surface of the sorbent transforms into an anionic form. Sharp increase in the sorption of strontium was observed when the equilibrium pH was between 7 and 10. This behavior could be attributed to the abrupt increase in net negative charge on the surface of the sorbent.

关键词： Sorption

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