咨询与建议

限定检索结果

文献类型

  • 49 篇 会议
  • 4 篇 期刊文献

馆藏范围

  • 53 篇 电子文献
  • 0 种 纸本馆藏

日期分布

学科分类号

  • 26 篇 工学
    • 17 篇 电子科学与技术(可...
    • 12 篇 化学工程与技术
    • 11 篇 电气工程
    • 9 篇 材料科学与工程(可...
    • 7 篇 冶金工程
    • 4 篇 计算机科学与技术...
    • 3 篇 动力工程及工程热...
    • 3 篇 信息与通信工程
    • 2 篇 力学(可授工学、理...
    • 2 篇 机械工程
    • 2 篇 仪器科学与技术
    • 2 篇 控制科学与工程
    • 2 篇 建筑学
    • 1 篇 土木工程
    • 1 篇 水利工程
    • 1 篇 纺织科学与工程
    • 1 篇 轻工技术与工程
  • 18 篇 理学
    • 11 篇 化学
    • 10 篇 物理学
    • 5 篇 数学
  • 1 篇 法学
    • 1 篇 社会学
  • 1 篇 管理学
    • 1 篇 管理科学与工程(可...

主题

  • 9 篇 etching
  • 6 篇 silicon
  • 5 篇 plasmas
  • 5 篇 flash memory
  • 4 篇 implants
  • 4 篇 large scale inte...
  • 4 篇 furnaces
  • 4 篇 oxidation
  • 4 篇 polymers
  • 3 篇 slurries
  • 3 篇 logic gates
  • 3 篇 dielectrics
  • 3 篇 copper
  • 3 篇 nitrogen
  • 3 篇 tin
  • 3 篇 stress
  • 3 篇 inspection
  • 3 篇 surface contamin...
  • 3 篇 cleaning
  • 2 篇 residual stresse...

机构

  • 7 篇 technology devel...
  • 2 篇 maintenance wet ...
  • 2 篇 advanced technol...
  • 2 篇 advanced packagi...
  • 2 篇 unit process dev...
  • 2 篇 wet module infin...
  • 2 篇 advanced process...
  • 2 篇 lsi logic inc. a...
  • 2 篇 automotive techn...
  • 2 篇 unit process eng...
  • 2 篇 process module d...
  • 2 篇 process integrat...
  • 2 篇 advanced device ...
  • 2 篇 process technolo...
  • 2 篇 defekt engineeri...
  • 2 篇 global reliabili...
  • 2 篇 key laboratory o...
  • 2 篇 unit process eng...
  • 2 篇 fujitsu laborato...
  • 2 篇 supplier quality...

作者

  • 14 篇 kuang-chao chen
  • 14 篇 tahone yang
  • 10 篇 chih-yuan lu
  • 9 篇 hong-ji lee
  • 8 篇 nan-tzu lian
  • 6 篇 sheng-yuan chang
  • 5 篇 burke peter
  • 5 篇 tuung luoh
  • 4 篇 kwak b. leo
  • 4 篇 sun sey-shing
  • 4 篇 chen kuang-chao
  • 4 篇 yang tahone
  • 4 篇 kuo-liang wei
  • 3 篇 w. catabay
  • 3 篇 j. lin
  • 3 篇 zusing yang
  • 3 篇 luoh tuung
  • 3 篇 v. hornback
  • 3 篇 j. pallinti
  • 3 篇 yuan-chieh chiu

语言

  • 50 篇 英文
  • 2 篇 其他
  • 1 篇 中文
检索条件"机构=Process Module Development"
53 条 记 录,以下是1-10 订阅
Numerical Study on the Influence of Polyimide Thickness and Curing Temperature on Wafer Bow in Wafer Level Packaging
Numerical Study on the Influence of Polyimide Thickness and ...
收藏 引用
作者: Singh, Prashant Kumar Rohlfs, Patrick Sandmann, Gunther Machani, Kashi Vishwanath Breuer, Dirk Meier, Karsten Kuechenmeister, Frank Wieland, Marcel Bock, Karlheinz Advanced Packaging Development GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Process Integration BEOL GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Institute of Electronic Packaging Technology Technische Universität Dresden Dresden Germany Global Reliability GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany
In wafer level packaging, polyimide and electroplated copper are dielectric and conducting materials respectively in the so-called redistribution layers. During the wafer fabrication process large amount of stress is ... 详细信息
来源: 评论
The incoming clean of raw silicon wafers: challenges, root causes and possible solutions  36
The incoming clean of raw silicon wafers: challenges, root c...
收藏 引用
36th Annual SEMI Advanced Semiconductor Manufacturing Conference, ASMC 2025
作者: Willnauer, Christa Konopatzky, Lorenz Landgraf, Andrea Büttner, Daniel Soella, Frank Assmann, Heiko Göhler, Jens Peters, Stefan Vater, Alfred Arnold, Frank Hummeltenberg, Anja Unit Process Engineering WET Infineon Technologies Dresden Dresden Germany Unit Process Development WET Infineon Technologies Dresden Dresden Germany Defekt Engineering Frontend Defectivity Infineon Technologies Dresden Dresden Germany Supplier Quality Management Infineon Technologies Dresden GmbH Dresden Germany Maintenance WET Infineon Technologies Dresden GmbH Dresden Germany Unit Process Engineering Waferinspection Infineon Technologies Dresden Dresden Germany Automotive Technology Development Infineon Technologies Dresden Dresden Germany WET Module Infineon Technologies Dresden Dresden Germany
An investigation of the cleaning efficiency of different raw wafer materials from different vendors is presented using a standard clean 1 and standard clean 2 incoming cleaning procedure. It will be discussed whether ... 详细信息
来源: 评论
Influence of Annealing on Microstructure of Electroplated Copper Trenches in Back-End-Of-Line
Influence of Annealing on Microstructure of Electroplated Co...
收藏 引用
IEEE International Conference on Interconnect Technology
作者: Prashant Kumar Singh Maik Müller Kashi Vishwanath Machani Dirk Breuer Michael Hecker Karsten Meier Frank Kuechenmeister Marcel Wieland Karlheinz Bock Advanced Packaging Development GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Institute of Electronic Packaging Technology Technische Universität Dresden Dresden Germany Process Integration BEOL GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Central Labs GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany Global Reliability GlobalFoundries Dresden Module One LLC & Co.KG Dresden Germany
Copper is widely used as an interconnect material in Back-End-of-Line (BEOL) because it has high thermal conductivity and good electromigration failure resistance. However, RF applications require a larger number of u...
来源: 评论
The incoming clean of raw silicon wafers: challenges, root causes and possible solutions
The incoming clean of raw silicon wafers: challenges, root c...
收藏 引用
IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing
作者: Christa Willnauer Lorenz Konopatzky Andrea Landgraf Daniel Büttner Frank Soella Heiko Assmann Jens Göhler Stefan Peters Alfred Vater Frank Arnold Anja Hummeltenberg Unit Process Engineering WET Infineon Technologies Dresden Dresden Germany Unit Process Development WET Infineon Technologies Dresden Dresden Germany Defekt Engineering Frontend Defectivity Infineon Technologies Dresden Dresden Germany Supplier Quality Management Infineon Technologies Dresden GmbH Dresden Germany Maintenance WET Infineon Technologies Dresden GmbH Dresden Germany Unit Process Engineering Waferinspection Infineon Technologies Dresden Dresden Germany Automotive Technology Development Infineon Technologies Dresden Dresden Germany WET Module Infineon Technologies Dresden Dresden Germany
An investigation of the cleaning efficiency of different raw wafer materials from different vendors is presented using a standard clean 1 and standard clean 2 incoming cleaning procedure. It will be discussed whether ... 详细信息
来源: 评论
A New Modulable Integrated Multi-Function Scan Driver for High-Resolution AMOLED Display with LTPS TFTs
A New Modulable Integrated Multi-Function Scan Driver for Hi...
收藏 引用
SID Symposium, Seminar, and Exhibition 2019, Display Week 2019
作者: Su, Yue Geng, Di Ji, Hansai Zhang, Xia Yu, Chaowei Xu, Xiangyang Takatori, Kenichi Li, Ling Liu, Ming Key Laboratory of Microelectronics Devices & Integrated Technology Institute of Microelectronics of Chinese Academy of Sciences Beijing100029 China Process Technology Development Dept of Huawei Technologies Co. Ltd. Shenzhen518129 China Display Module Technology Lab. of Huawei Technologies Japan K.K. Yokohama221-0056 Japan
We proposed a modulable integrated multi-function scan driver for active-matrix organic light-emitting diode (AMOLED) display based on low-temperature-poly-Si thin-film transistors (LTPS TFTs). The proposed circuit pr... 详细信息
来源: 评论
ANYSYS Chip-Level and Wafer-Level Simulation on Semiconductor process development - Yu-Chih Chang
ANYSYS Chip-Level and Wafer-Level Simulation on Semiconducto...
收藏 引用
2017 Joint International Symposium on e-Manufacturing and Design Collaboration, eMDC 2017 and Semiconductor Manufacturing, ISSM 2017
作者: Chen, Chi-Min Hung, Yung-Tai Luoh, Tuung Yang, Tahone Chen, Kuang-Chao Macronix International Co. Ltd Technology Development Center Advanced Module Process Development Div. No. 19 Li-Hsin Road Science Park Hsin-chu Taiwan
Most of simulation activities implemented on semiconductor manufacturing are focus on the device characteristics, and electrical properties. Less investigation pays attention on micro-structure stress/strain calculati... 详细信息
来源: 评论
Study of Ti/TiN bump defect formation mechanism and elimination by etch process optimization
Study of Ti/TiN bump defect formation mechanism and eliminat...
收藏 引用
IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing
作者: Li-Lan Wu Yuan-Chieh Chiu Zusing Yang Sheng-Yuan Chang Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Advanced Module Process Development Div Technology Development Center Taiwan ROC
Subtle Ti/TiN bump defects are observed after thermal annealing in the development step of a back-end-of-line (BEOL) via metallization. It disturbs the endpoint detection of a sequential tungsten (W) chemical-mechanic... 详细信息
来源: 评论
Nano-scale scratch impact on 7nm device and its improvement by predictable CMP process conditions
Nano-scale scratch impact on 7nm device and its improvement ...
收藏 引用
2017 International Conference on Planarization/CMP Technology, ICPT 2017
作者: Yang, Ji Chul Penigalapati, Dinesh Kumar Lu, Wen Yin Cho, Tai Fong Snyder, Alison Koli, Dinesh CMP Process Development Team Advanced Module Engineering GLOBALFOUNDRIES 400 Stonebreak Road Extension MaltaNY12020 United States CMP Unit Process Manufacturing Team Advanced Module Engineering GLOBALFOUNDRIES 400 Stonebreak Road Extension MaltaNY12020 United States
来源: 评论
Asymmetric etching profile control during high aspect ratio Plasma etch
Asymmetric etching profile control during high aspect ratio ...
收藏 引用
IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing
作者: Zusing Yang Li-Ian Wu Sheng-Yuan Chang Yuan-Chieh Chiu Hong-Ji Lee Nan-Tzu Lian Tahone Yang Kuang-Chao Chen Chih-Yuan Lu Hayato Watanabe Yinhwa Cheng Takao Arase Masahito Mori Macronix International Co. Ltd. Advanced Module Process Development Div. Taiwan ROC Hitachi High-Technologies Corporation Japan Hitachi High-Technologies Taiwan Corporation Taiwan
Dependency of asymmetric etched profiles on open-ratio and pattern-size within the wafer was studied in a magnetic Very High Frequency (VHF) Plasma etching system for high aspect-ratio multiple alternating layers of s... 详细信息
来源: 评论
A Promising Solution to Reduce Plasma Induced Damage (PID) of High Density Plasma (HDP) Oxide without Sacrificing the Gap-fill and Throughput Performance - Chin-Tsan Yeh
A Promising Solution to Reduce Plasma Induced Damage (PID) o...
收藏 引用
2017 Joint International Symposium on e-Manufacturing and Design Collaboration, eMDC 2017 and Semiconductor Manufacturing, ISSM 2017
作者: Yu, Chia-Sheng Chen, Ying-Tso Shih, Yen-Hao Lu, Chih-Yuan Macronix International Co. Ltd. Foundry Business Group Process Module Development Dept. No. 16 Li-Hsin Road Science-Based Industrial Park Hsinchu Taiwan
Plasma induced damage (PID) during high density plasma (HDP) chemical vapor deposition (CVD) deposition is a challenge for fabricating metal oxide semiconductor field effect transistors (MOSFETs). In this paper, reduc... 详细信息
来源: 评论