In wafer level packaging, polyimide and electroplated copper are dielectric and conducting materials respectively in the so-called redistribution layers. During the wafer fabrication process large amount of stress is ...
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An investigation of the cleaning efficiency of different raw wafer materials from different vendors is presented using a standard clean 1 and standard clean 2 incoming cleaning procedure. It will be discussed whether ...
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Copper is widely used as an interconnect material in Back-End-of-Line (BEOL) because it has high thermal conductivity and good electromigration failure resistance. However, RF applications require a larger number of u...
Copper is widely used as an interconnect material in Back-End-of-Line (BEOL) because it has high thermal conductivity and good electromigration failure resistance. However, RF applications require a larger number of ultra-thick copper metals combined with a high metal density. Due to high CTE mismatch of the copper interconnects to silicon a high wafer bow is induced during the BEOL process steps. A main contribution for the high wafer bow is the stress induced in the wafer due to annealing process steps at elevated temperature. The current study focuses on the effect of line width and annealing temperatures on stress relaxation and microstructural evolution due to aging for one month. In addition, the effect of microstructural change is studied with the time dependent wafer bow measurement showing stress relaxation over time.
An investigation of the cleaning efficiency of different raw wafer materials from different vendors is presented using a standard clean 1 and standard clean 2 incoming cleaning procedure. It will be discussed whether ...
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ISBN:
(数字)9798331531850
ISBN:
(纸本)9798331531867
An investigation of the cleaning efficiency of different raw wafer materials from different vendors is presented using a standard clean 1 and standard clean 2 incoming cleaning procedure. It will be discussed whether the observed material and vendor dependency is caused by the incoming clean, the used manufacturing tools or by the wafer material itself. By using particle and contact angle measurements, QCEPT, REM and EDX, significant variations of the raw wafer surface were found before and after the incoming clean. Thus, an analysis of the entire raw wafer supply chain was performed including production, packaging, transport and unpackaging of the wafers. A determination of the root cause of the observed cleaning inefficiencies was possible and solutions to overcome the apparent cleaning inefficiency could be derived.
We proposed a modulable integrated multi-function scan driver for active-matrix organic light-emitting diode (AMOLED) display based on low-temperature-poly-Si thin-film transistors (LTPS TFTs). The proposed circuit pr...
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Most of simulation activities implemented on semiconductor manufacturing are focus on the device characteristics, and electrical properties. Less investigation pays attention on micro-structure stress/strain calculati...
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Subtle Ti/TiN bump defects are observed after thermal annealing in the development step of a back-end-of-line (BEOL) via metallization. It disturbs the endpoint detection of a sequential tungsten (W) chemical-mechanic...
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Subtle Ti/TiN bump defects are observed after thermal annealing in the development step of a back-end-of-line (BEOL) via metallization. It disturbs the endpoint detection of a sequential tungsten (W) chemical-mechanical planarization (CMP) process and results in W residue on the surface of the wafer. SIMS analysis conducted before Ti/TiN deposition indicates the presence of high concentrations of fluorine (F) atoms that have already doped into the oxide film after the via hole plasma etching process, even in the presence of an amorphous carbon hard-mask. The doped F species could diffuse out of the surface region, and then react with as-deposited Ti/TiN to form volatile TiF 4 during high-temperature annealing. As a result, severe metallic bump-like defects are observed. In this study, we report that the formation of the metallic bump defect is correlated to both the RF bias frequency, and the RF bias power applied in the capacitive-coupled fluorocarbon plasma via feature etching.
Dependency of asymmetric etched profiles on open-ratio and pattern-size within the wafer was studied in a magnetic Very High Frequency (VHF) Plasma etching system for high aspect-ratio multiple alternating layers of s...
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Dependency of asymmetric etched profiles on open-ratio and pattern-size within the wafer was studied in a magnetic Very High Frequency (VHF) Plasma etching system for high aspect-ratio multiple alternating layers of silicon oxide/polysilicon (OP) etching. The etched physical features are sensitive to the overall open ratio on the wafer; the profile sidewalls became bent while the open ratio changed from 8% to 40%. In this study, the profile recovery from a method of design of experiments (DOE) and specific inductively magnetic field applied in the etching system was explored. The resulting etched profile is successfully back to normal on multi-layered OP film stack at 40% of open ratio. Even at next generation node development, the etching based on DOE also demonstrates good shape control on the etched profile which stacked with OP pairs over 3um in thickness in extremely high aspect ratio trench etching.
Plasma induced damage (PID) during high density plasma (HDP) chemical vapor deposition (CVD) deposition is a challenge for fabricating metal oxide semiconductor field effect transistors (MOSFETs). In this paper, reduc...
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