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Proceedings of the ACM Symposium on Applied Computing 2007年 1565-1572页

作者： Kyung, Hyun-Min Park, Gi-Ho Kwak, Jong Wook Jeong, Wookyeong Kim, Tae-Jin Park, Sung-Bae Processor Architecture Lab. System LSI Division SOC R and D Center Yongin-City Kyeong-gi Do Korea Republic of

ISBN: (纸本)1595934804;9781595934802

As the physical gate-count in system-On-Chip (SOC) system increases and system design complexity grows steadily, it becomes more and more difficult to achieve good resource utilization by assigning each task to certain hardware IP and tracing the execution patterns of each task efficiently. Therefore, the performance monitoring feature is getting more and more important to provide the ease of system monitoring and performance debugging. In this paper, we present a performance monitoring unit (PMU) for the AMBA Advanced eXtensible Interface (AXI) bus. The PMU has capability to measure major performance metrics, such as bus latency for the specific master requests and amount of memory traffic for specific durations. It can also measure the contention of the bus masters and slaves in the SOC. We present the distributor and the synchronization method to use multiple performance counting units as well. The performance monitoring unit has been verified in the platform FPGA board with 9 by 4 AXI interconnect configuration. These monitoring features can give the insight to system design architect by helping to find and analyze the performance bottleneck of target system. Copyright 2007 ACM.

关键词： systems analysis

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An Efficient Scheme for Parallelizing Fast Search Algorithm on SIMD architecture in H.264/AVC 20

An Efficient Scheme for Parallelizing Fast Search Algorithm ...

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20th International Conference on Parallel and Distributed Computing systems, PDCS 2007

作者： Park, Jung-Min Park, Jung-Wook Kim, Cheong-Ghil Park, Gi-Ho Kim, Shin-Dug Department of Computer Science Yonsei University Seoul Korea Republic of Processor Architecture Lab. System LSI Division Samsung Electronics Co. Ltd Giheung Korea Republic of

ISBN: (纸本)9781604233926

As the video CODECs become complex increasingly according to the convergence of digital equipments designed for different kinds of specific purposes, the demand of higher performance for video processing is continuously needed. The fast search methods are well known as a representative approach to overcome the performance bottleneck of video encoding. But they require huge computations and dominate most of the running time of video encoding. So, a parallel processing is required to enhance the performance. In general, the fast search methods are difficult to be parallelized because their memory access patterns are not followed by a definite form. This paper proposes a new method for parallelizing a fast search method using linear SIMD architecture with only one-to-one connection between a PE and a memory bank. The simulation results show that the proposed method can reduce nearly 20 percent of running time in the motion estimation (ME). © 20th International Conference on Parallel and Distributed Computing systems, PDCS 2007. All rights reserved.

关键词： Motion estimation

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Power-aware deterministic block allocation for low-power way-selective cache structure

Power-aware deterministic block allocation for low-power way...

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Proceedings - IEEE International Conference on Computer Design: Vlsi in Computers and processors, ICCD 2004

作者： Park, Jung-Wook Park, Gi-Ho Park, Sung-Bae Kim, Shin-Dug CS Yonsei University 134 Shinchon-dong Seoul 120-749 Korea Republic of Processor Architecture Lab. System LSI Division Samsung Electronics Co. Ltd. Giheung Korea Republic of

This paper proposes a power-aware cache block allocation algorithm for the way-selective set-associative cache on embedded systems to reduce energy consumption without additional delay or performance degradation. For this goal, way selection logic and specialized replacement policy are designed to enable only one way of set-associative cache as in the direct-mapped cache. Overall cache access time becomes almost the same as that of conventional set associative cache with accessing additional way selection logic. Because data array can be accessed without waiting for tag comparison, multiplexer delay can be removed totally. The simulation result shows that the proposed architecture can reduce a per access power consumption by 59% over conventional set-associative caches with average 0.06% of negligible performance loss. © 2004 IEEE.

关键词： Buffer storage

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Practice and experience of an embedded processor core modeling

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2nd International Conference on High Performance Computing and Communications, HPCC 2006

作者： Park, Gi-Ho Sung, Woo Chung Kim, Han-Jong Im, Jung-Bin Park, Jung-Wook Kim, Shin-Dug Park, Sung-Bae Processor Architecture Lab. SOC R and D Center System LSI Division Kyeonggi-Do Korea Republic of Division of Computer and Communication Engineering Korea University Anam-Dong Seongbuk-Gu Seoul Korea Republic of Supercomputing Lab. Yonsei University 134 Shinchon-Dong Seodaemun-Gu Seoul Korea Republic of

ISBN: (纸本)3540393684

This paper presents our experience in developing an embedded processor core model for an SOC design. We developed an ARM1136 processor simulation environment based on the ARM's MaxCore tool and the SimpleScaclar simulator. A MaxCore ARM1136 instruction accurate (IA) model is developed to support application programmers for the writing application programs from the early design stage. The MaxCore ARM1136 processor model supports all ARMv4, ARMv5TE and ARM v6 instruction sets with 418 LISA instructions. This MaxCore IA Model can be integrated with the ARM's MaxSim system level design environment to develop application softwares and perform architecture explorations. A SimpleScalar ARM1136 cycle accurate (CA) model is also developed by enhancing the existing SimpleScalar-ARM version in the SimpleScalar 3.0. Most important micro-architectural features of ARM1136 processor are implemented in the enhanced SimpleScalar simulator. The accuracy of the developed SimpleScalar-ARM 1136 simulator is about 97% compared to ARM 1136 RTL simulation with the Dhrystone benchmark (100 iterations). © Springer-Verlag Berlin Heidelberg 2006.

关键词： Embedded systems

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