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MLEA： A Solution for Users of Android in UTPVirtual

computer Technology and Application 2011年第5期2卷 406-412页

作者： Gisela Torres de Clunie Sergio Crespo Coelho da Silva Pinto Aris Linet Castillo Lucas Monteiro Braz Tasia Serrao Norman Rangel Jeanette Riley Olinda de Barraza Kexy Rodriguez Computer Systems Engineering Department Technological University of Panama Panama 0819 Panama Computer Science Research and Graduate Program in Applied Computing University of the Sinos Valley （UNISINOS） RS 93022-000 Brazil CIDITIC Technological University of Panama Panama 0819 Panama

This paper describes a design of an educational platform for a mobile learning architecture, which is a state of the an topic in distance education. The product will allow users to interact in an efficient, flexible, and transparent fashion with a web-based education environment, in this case Module Object-Oriented Dynamic Learning Environment （Moodle）, using Android mobile devices. In order to provide a strong and lasting architecture, the Service Oriented Architecture （SOA） methodology is used given that it allows easy software re-utilization as well as integration of heterogeneous services. The architecture is based on web services implemented with Representational State Transfer （REST）, as it has been demonstrated to be lighter and less consuming than other protocols, for devices with limited resources such as mobile devices. Web services provide the communication means between the server side and the client side of the architecture, whereas agents are used to deliver the services itself. The authors propose the development of an environment that facilitates the integration of various educational resources to support m-learning. An important aspect of the proposal is the offering of a tool to provide customized alerts for students and teachers, enabling them to remain updated about activities taking place in the courses.

关键词： Distance learning virtual education m-learning service oriented architecture （SOA） mobile learning mobile computing interoperability representational state transfer （REST）.

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Structure and magnetic properties characterization of electrodeposited Co37Fe63 alloys containing oxygen for magnetic recording applications

Structure and magnetic properties characterization of electr...

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作者： Elhalawaty, S. Carpenter, R.W. George, J. Brankovic, S.R. Materials Science and Engineering Graduate Program School for Engineering of Matter Transport and Energy Arizona State University 85287-6106 United States LeRoy Eyring Center for Solid State Science Arizona State University AZ 85287-9506 United States Center for Nanomagnetic Systems University of Houston TX 77204-4005 United States Electrical and Computer Engineering Department University of Houston TX 77204-4005 United States

ISBN: (纸本)9781118029473

Soft and high magnetic moment Co37Fe63 films were electro-deposited with variable additives on Cu/Ti/Si substrates. The correlation between structure and magnetic properties has been investigated. TEM showed the crystal structure of the films to be BCC with a 〈111〉 texture, and a grain size in the range of 10-20 nm. Oxygen in the deposited films has been identified by EDS and EELS using HAADF STEM. SIMS analysis revealed the presence of hydrogen and oxygen in the deposited CoFe films. Electron microscopy results showed that the oxygen was mainly distributed along the grain boundaries in the CoFe film. In regions where oxygen was present in the films, the Fe content was enhanced relative to Co. The magnetic properties of the deposits have been measured by Vibrating Sample Magnetometer (VSM), quantifying the impact of incorporated oxygen in the film on the saturation magnetization and the coercivity.

关键词： Magnetic properties

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A parallel architecture for ray-tracing with an embedded intersection algorithm

A parallel architecture for ray-tracing with an embedded int...

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IEEE International Symposium on Circuits and systems (ISCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M.G. França Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhovan University of Technology Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro (UERJ) Brazil

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.

关键词： Ray tracing Registers Equations USA Councils Mathematical model Parallel architectures

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Comparison of disturbance rejection performance between sliding-mode control and equivalent-input-disturbance approach

Comparison of disturbance rejection performance between slid...

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IEEE International Conference on Mechatronics

作者： She, Jinhua Pan, Yaodong Hashimoto, Hiroshi Wu, Min School of Computer Science Tokyo Univ. of Tech. Hachioji 192-0982 Japan Control Systems Eng Honeywell Canada Mississauga ON L5L3S6 Canada Master Program of Innovation for Design and Eng Advanced Institute of Industrial Tech. Tokyo 140-0011 Japan School of Information Science and Engineering Central South Univ. Changsha 410083 China

ISBN: (纸本)9781612849836

Sliding mode control (SMC) has been considered as a powerful method for disturbances rejection. On the other hand, we have presented an equivalent-input disturbance (EID) approach to reject disturbances. This paper takes a dual-stage feed drive as an example to compare these two methods. The example shows that, while the EID approach obtains almost the same disturbance rejection performance for matched disturbances as that of the SMC does, it can reject unmatched disturbances. This shows the superiority of the EID approach over SMC method. © 2011 IEEE.

关键词： Sliding mode control

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A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations

A Parallel Ray Tracing Architecture Suitable for Application...

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Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Nadia Nedjah Felipa M.G. Franca Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Universidade do Estado do Rio de Janeiro Rio de Janeiro RJ BR

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared.

关键词： Ray tracing Graphics processing unit Instruction sets computer architecture Registers Image color analysis Hardware

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Complex-valued functional link network design by orthogonal least squares method for function approximation problems

Complex-valued functional link network design by orthogonal ...

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International Joint Conference on Neural Networks (IJCNN)

作者： Md. Faijul Amin Ramasamy Savitha Muhammad Ilias Amin Kazuyuki Murase Department of Systems Design Engineering Graduate School of Engineering University of Fukui Fukui Japan School of Electrical and Electronics Engineering Nanyang Technological University Singapore Department of Computer Science and Engineering United International University Dhaka Bangladesh Research and Education Program for Life Science University of Fukui Fukui Japan

This paper presents a fully complex-valued functional link network (CFLN). The CFLN is a single-layered neural network, which introduces nonlinearity in the input layer using nonlinear functions of the original input variables. In this study, we consider multivariate polynomials as the nonlinear functions. Unlike multilayer neural networks, the CFLN is free from local minima problem, and it offers very fast learning in parameters because of its linear structure. In the complex domain, polynomial based CFLN has an additional advantage of not requiring activation functions, which is a major concern in the complex-valued neural networks. However, it is important to select a smaller subset of polynomial terms (monomials) for faster and better performance, since the number of all possible monomials may be quite large. In this paper, we use the orthogonal least squares method in a constructive fashion (starting from lower degree to higher) for the selection of a parsimonious subset of monomials. Simulation results demonstrate that computing CFLN in purely complex domain is advantageous than in double-dimensional real domain, in terms of number of connection parameters, faster design, and possibly generalization performance. Moreover, our proposed CFLN compares favorably with several other multilayer networks in the complex domain.

关键词： Polynomials Nonhomogeneous media Educational institutions Algorithm design and analysis Function approximation Neural networks Input variables

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Low-Frequency Noise in “Graphene-Like” Exfoliated Thin Films of Topological Insulators

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MRS Online Proceedings Library 2011年第1期1344卷 1-5页

作者： M. Z. Hossain S. L. Rumyantsev K. M. F. Shahil D. Teweldebrhan M. Shur A. A. Balandin Nano-Device Laboratory Department of Electrical Engineering and Materials Science and Engineering Program University of California Riverside USA Department of Electrical Computer and Systems Engineering and Center for Integrated Electronics Rensselaer Polytechnic Institute Troy USA Ioffe Institute Russian Academy of Sciences St. Petersburg Russia

We report results of the study of the low-frequency noise in thin films of bismuth selenide topological insulators, which were mechanically exfoliated from bulk crystals via “graphene-like” procedures. From the resistance dependence on the film thickness, it was established that the surface conduction contributions to electron transport were dominant. It was found that the current fluctuations have the noise spectral density SI ∞ 1/ f (where f is the frequency) for the frequency range up to 10 kHz. The obtained noise data are important for transport experiments with topological insulators and for any proposed device applications of these materials.

关键词： devices electrical properties thin film

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Hardware Reuse in Modern Application-Specific Processors and Accelerators

Hardware Reuse in Modern Application-Specific Processors and...

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Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Lech Jozwiak Menno Lindwer Mauro Cocco Nadia Nedjah Felipe M.G. Franca LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive-Intel UMG Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

关键词： Hardware Resource management computer architecture Optimization program processors Adders Delay

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LOW-FREQUENCY ELECTRONIC NOISE IN GRAPHENE TRANSISTORS: COMPARISON WITH CARBON NANOTUBES

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International Journal of High Speed Electronics and systems 2011年第1期20卷 161-170页

作者： GUANXIONG LIU WILLIAM STILLMAN SERGEY RUMYANTSEV MICHAEL SHUR ALEXANDER A. BALANDIN Nano-Device Laboratory Department of Electrical Engineering Materials Science and Engineering Program Bourns College of Engineering University of California – Riverside Riverside California 92521 USA Center for Integrated Electronics and Department of Electrical Computer and Systems Engineering Rensselaer Polytechnic Institute Troy New York 12180 USA Ioffe Physico-Technical Institute Russian Academy of Sciences St. Petersburg 194021 Russia Nano-Device Laboratory Department of Electrical Engineering and Materials Science Engineering Program Bourns College of Engineering University of California – Riverside Riverside California 92521 USA

We report results of the experimental investigation of the low-frequency noise in graphene transistors. The graphene devices were measured in three-terminal configuration. The measurements revealed low flicker noise levels with the normalized noise spectral density close to 1/f (f is the frequency) and the Hooge parameter α H ~10 -3 . Both top-gate and back-gate devices were studied. The analysis of the noise spectral-density dependence on the gate biases helped us to elucidate the noise sources in these devices. We compared the noise performance of graphene devices with that of carbon nanotube devices. It was determined that graphene devices works better than carbon nanotube devices in terms of the low-frequency noise. The obtained results are important for graphene electronic, communication and sensor applications.

关键词： graphene 1/ f noise carbon nanotubes low-frequency noise graphene transistors

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Hardware Particle Swarm Optimization with passive congregation for embedded applications

Hardware Particle Swarm Optimization with passive congregati...

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Southern Conference on programmable Logic

作者： Daniel M. Muñoz Carlos H. Llanos Leandro dos S. Coelho Mauricio Ayala-Rincón Department of Mechanical Engineering Automation and Control Group/GRACO University of Brasilia Brazil Industrial and Systems Engineering Graduate Program LAS/PPGPES Pontifical Catholic University of Paraná Curitiba Parana Brazil Department of Computer Science and Mathematics University of Brasilia Brazil

Achieving high performance optimization algorithms for embedded applications can be very challenging, particularly when several requirements such as high accuracy computations, short elapsed time, area cost, low power consumption and portability must be accomplished. This paper proposes a hardware implementation of the Particle Swarm Optimization algorithm with passive congregation (HPPSOpc), which was developed using several floating-point arithmetic libraries. The passive congregation is a biological behavior which allows the swarm to preserve its integrity, balancing between global and local search. The HPPSOpc architecture was implemented on a Virtex5 FPGA device and validated using two multimodal benchmark problems. Synthesis, simulation and execution time results demonstrates that the passive congregation approach is a low cost solution for solving embedded optimization problems with a high performance.

关键词： Hardware computer architecture Software Field programmable gate arrays Benchmark testing Optimization Software algorithms

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