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Leakage-Aware Modulo Scheduling for Embedded VLIW Processors

Journal of Computer Science & Technology 2011年第3期26卷 405-417页

作者：关永薛京灵 College of Information Engineering Capital Normal University Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales

As semi-conductor technologies move down to the nanometer scale, leakage power has become a significant component of the total power consumption. In this paper, we present a leakage-aware modulo scheduling algorithm to achieve leakage energy saving for applications with loops on Very Long Instruction Word （VLIW） architectures. The proposed algorithm is designed to maximize the idleness of function units integrated with the dual-threshold domino logic, and reduce the number of transitions between the active and sleep modes. We have implemented our technique in the Trimaran compiler and conducted experiments using a set of embedded benchmarks from DSPstone and Mibench on the cycle-accurate VLIW simulator of Trimaran. The results show that our technique achieves significant leakage energy saving compared with a previously published DAG-based （Directed Acyclic Graph） leakage-aware scheduling algorithm.

关键词： leakage power very long instruction word (VLIW) software pipelining modulo scheduling

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Static memory leak detection using full-sparse value-flow analysis

Static memory leak detection using full-sparse value-flow an...

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21st International Symposium on Software Testing and Analysis, ISSTA 2012

作者： Sui, Yulei Ye, Ding Xue, Jingling Programming Languages and Compilers Group School of Computer Science and Engineering UNSW Australia

ISBN: (纸本)9781450314541

We introduce a static detector, Saber, for detecting memory leaks in C programs. Leveraging recent advances on sparse pointer analysis, Saber is the first to use a full-sparse value-flow analysis for leak detection. Saber tracks the flow of values from allocation to free sites using a sparse value-flow graph (SVFG) that captures def-use chains and value flows via assignments for all memory locations represented by both top-level and address-taken pointers. By exploiting field-, flow- and context-sensitivity during different phases of the analysis, Saber detects leaks in a program by solving a graph reachability problem on its SVFG. Saber, which is fully implemented in Open64, is effective at detecting 211 leaks in the 15 SPEC2000 C programs and five applications, while keeping the false positive rate at 18.5%. We have also compared Saber with Fastcheck (which analyzes allocated objects flowing only into top-level pointers) and Sparrow (which handles all allocated objects using abstract interpretation) using the 15 SPEC2000 C programs. Saber is as accurate as Sparrow but is 14.2X faster and reports 40.7% more bugs than Fastcheck at a slightly higher false positive rate but is only 3.7X slower. © 2012 ACM.

关键词： Flow graphs

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PartialRC: A Partial Recomputing Method for Efficient Fault Recovery on GPGPUs

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Journal of Computer Science & Technology 2012年第2期27卷 240-255页

作者：徐新海杨学军薛京灵林宇斐林一松 National Laboratory for Parallel and Distributed Processing School of ComputerNational University of Defense Technology Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales

GPGPUs are increasingly being used to as performance accelerators for HPC （High Performance Computing） applications in CPU/GPU heterogeneous computing systems, including TianHe-1A, the world＇s fastest supercomputer in the TOP500 list, built at NUDT （National University of Defense Technology） last year. However, despite their performance advantages, GPGPUs do not provide built-in fault-tolerant mechanisms to offer reliability guarantees required by many HPC applications. By analyzing the SIMT （single-instruction, multiple-thread） characteristics of programs running on GPGPUs, we have developed PartialRC, a new checkpoint-based compiler-directed partial recomputing method, for achieving efficient fault recovery by leveraging the phenomenal computing power of GPGPUs. In this paper, we introduce our PartialRC method that recovers from errors detected in a code region by partially re-computing the region, describe a checkpoint-based faulttolerance framework developed on PartialRC, and discuss an implementation on the CUDA platform. Validation using a range of representative CUDA programs on NVIDIA GPGPUs against FullRC （a traditional full-recomputing Checkpoint-Rollback-Restart fault recovery method for CPUs） shows that PartialRC reduces significantly the fault recovery overheads incurred by FullRC, by 73.5% when errors occur earlier during execution and 74.6% when errors occur later on average. In addition, PartialRC also reduces error detection overheads incurred by FullRC during fault recovery while incurring negligible performance overheads when no fault happens.

关键词： GPGPU partial recomputing fault tolerance CUDA checkpointing

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Adaptive detection of design flaws

Adaptive detection of design flaws

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作者： Kreimer, Jochen Research Group Programming Languages and Compilers Department of Computer Science University of Paderborn Germany

Criteria for software quality measurement depend on the application area. In large software systems criteria like maintainability, comprehensibility and extensibility play an important role. My aim is to identify design flaws in software systems automatically and thus to avoid "bad" - incomprehensible, hardly expandable and changeable - program structures. Depending on the perception and experience of the searching engineer, design flaws are interpreted in a different way. I propose to combine known methods for finding design flaws on the basis of metrics with machine learning mechanisms, such that design flaw detection is adaptable to different views. This paper presents the underlying method, describes an analysis tool for Java programs and shows results of an initial case study. © 2005 Elsevier B.V. All rights reserved.

关键词： Computer software

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Toward harnessing DOACROSS parallelism for multi-GPGPUs

Toward harnessing DOACROSS parallelism for multi-GPGPUs

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International Conference on Parallel Processing

作者： Di, Peng Wan, Qing Zhang, Xuemeng Wu, Hui Xue, Jingling Programming Languages and Compilers Group School of Computer Science and Engineering UNSW Sydney NSW 2052 Australia

ISBN: (纸本)9780769541563

To exploit the full potential of GPGPUs for generalpurpose computing, DOACR parallelism abundant in scientific and engineering applications must be harnessed. However, the presence of cross-iteration data dependences in DOACR loops poses an obstacle to execute their computations concurrently using a massive number of fine-grained threads. This work focuses on iterative PDE solvers rich in DOACR parallelism to identify optimization principles and strategies that allow their efficient mapping to GPGPUs. Our main finding is that certain DOACR loops can be accelerated further on GPGPUs if they are algorithmically restructured (by a domain expert) to be more amendable to GPGPU parallelization, judiciously optimized (by the compiler), and carefully tuned by a performance-tuning tool. We substantiate this finding with a case study by presenting a new parallel SSOR method that admits more efficient data-parallel SIMD execution than red-black SOR on GPGPUs. Our solution is obtained non-conventionally, by starting from a K-layer SSOR method and then parallelizing it by applying a non-dependencepreserving scheme consisting of a new domain decomposition technique followed by a generalized loop tiling. Despite its relatively slower convergence, our new method outperforms red-black SOR by making a better balance between data reuse and parallelism and by trading off convergence rate for SIMD parallelism. Our experimental results highlight the importance of synergy between domain experts, compiler optimizations and performance tuning in maximizing the performance of applications, particularly PDE-based DOACR loops, on GPGPUs. © 2010 IEEE.

关键词： Iterative methods

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A Lifetime Optimal Algorithm for Speculative PRE

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ACM Transactions on Architecture and Code Optimization 2006年第2期3卷 115-155页

作者： Xue, Jingling Cai, Qiong University of New South Wales Programming Languages and Compilers Group School of Computer Science and Engineering Sydney NSW 2052 Australia

A lifetime optimal algorithm, called MC-PRE, is presented for the first time that performs speculative PRE based on edge profiles. In addition to being computationally optimal in the sense that the total number of dynamic computations for an expression in the transformed code is minimized, MC-PRE is also lifetime optimal since the lifetimes of introduced temporaries are also minimized. The key in achieving lifetime optimality lies not only in finding a unique minimum cut on a transformed graph of a given CFG, but also in performing a data-flow analysis directly on the CFG to avoid making unnecessary code insertions and deletions. The lifetime optimal results are rigorously proved. We evaluate our algorithm in GCC against three previously published PRE algorithms, namely,MC-PREcomp (Qiong and Xue’s computationally optimal version of MC-PRE), LCM (Knoop, R¨ uthing, and Steffen’s lifetime optimal algorithm for performing nonspeculative classic PRE), and CMP-PRE (Bodik, Gupta, and Soffa’s PRE algorithm based on code-motion preventing (CMP) regions, which is speculative but not computationally optimal). We report and analyze our experimental results, obtained from both actual program execution and instrumentation, for all 22 C, C++ and FORTRAN 77 benchmarks from SPECcpu2000 on an Itanium 2 computer system. Our results show that MC-PRE (or MC-PREcomp) is capable of eliminating more partial redundancies than both LCM and CMP-PRE (especially in functions with complex control flow), and, in addition, MC-PRE inserts temporaries with shorter lifetimes than MC-PREcomp. Each of both benefits has contributed to the performance improvements in benchmark programs at the costs of only small compile-time and code-size increases in some benchmarks. © 2006, ACM. All rights reserved.

关键词： Algorithms Classic PRE Computational optimality Data-flow analysis Experimentation languages Lifetime optimality Partial redundancy elimination Performance Speculative PRE

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PARBLO:Page-Allocation-Based DRAM Row Buffer Locality Optimization

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Journal of Computer Science & Technology 2009年第6期24卷 1086-1097页

作者：米伟冯晓兵贾耀仓陈莉薛京灵 Key Laboratory of Computer System and Architecture Institution of Computing Technology Chinese Academy of Sciences Graduate University of Chinese Academy of Sciences Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales

DRAM row buffer conflicts can increase memory access latency significantly. This paper presents a new pageallocation-based optimization that works seamlessly together with some existing hardware and software optimizations to eliminate significantly more row buffer conflicts. Validation in simulation using a set of selected scientific and engineering benchmarks against a few representative memory controller optimizations shows that our method can reduce row buffer miss rates by up to 76% （with an average of 37.4%）. This reduction in row buffer miss rates will be translated into performance speedups by up to 15% （with an average of 5%）.

关键词： DRAM row buffer page allocation locality optimization

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On ownership and accessibility

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20th European Conference on Object-Oriented programming, ECOOP 2006

作者： Lu, Yi Potter, John Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales Sydney Australia

ISBN: (纸本)3540357262

Ownership types support information hiding by providing statically enforceable object encapsulation based on an ownership tree. However ownership type systems impose fixed ownership and an inflexible access policy. This paper proposes a novel type system which generalizes ownership types by separating object accessibility and reference capability. With the ability to hide owners, it provides a more flexible and useful model of object ownership. © Springer-Verlag Berlin Heidelberg 2006.

关键词： Object oriented programming

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Accelerating dynamic detection of uses of undefined values with static value-flow analysis

Accelerating dynamic detection of uses of undefined values w...

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12th ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2014

作者： Ye, Ding Sui, Yulei Xue, Jingling Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales NSW 2052 Australia

ISBN: (纸本)9781450326704

Uninitialized variables can cause system crashes when used and security vulnerabilities when exploited. With source rather than binary instrumentation, dynamic analysis tools such as MSan can detect uninitialized memory uses at significantly reduced overhead but are still costly. In this paper, we introduce a static value-flow analysis, called Usher, to guide and accelerate the dynamic analysis performed by such tools. Usher reasons about the definedness of values using a value-flow graph (VFG) that captures def-use chains for both top-level and address-taken variables interprocedurally and removes unnecessary instrumentation by solving a graph reachability problem. Usher works well with any pointer analysis (done a priori) and facilitates advanced instrumentation-reducing optimizations (with two demonstrated here). Implemented in LLVM and evaluated using all the 15 SPEC2000 C programs, Usher can reduce the slowdown of MSan from 212% - 302% to 123% - 140% for a number of configurations tested. Copyright © 2014 by the Association for Computing Machinery, Inc. (ACM).

关键词： Flow graphs

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Compiler-directed scratchpad memory management

Compiler-directed scratchpad memory management

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ICESS 2005 - 2nd International Conference on Embedded Software and Systems

作者： Jingling, Xue Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales Sydney NSW 2052 Australia

ISBN: (纸本)0769525121

On-chip memory, in the form of (hardware-managed) cache,(software-managed) scratchpad memory (SPM) or some combination of both, is widely used in embedded systems. Most high-end embedded systems have both cache and SPM on-chip since each addresses a different need. Caches allow easy integration and are often effective but are un-predictable. SPMs are more energy-efficient than caches since they do not need complex tag-decoding logic. In addition, SPMs provide absolutely predictable performance but the programmer or compiler must schedule explicit data/instruction transfers between the SPM and off-chip main memory in an embedded system. In today's industry, this task is largely accomplished manually. The programmer often spends a lot of time on partitioning data and/or instructions and inserting explicit data/instruction transfers required between the SPM and main memory. Such a manual approach is time-consuming and error-prone. Obtaining satisfactory solutions for large application programs by hand can be challenging. Furthermore, hand-crafted code is not portable since it is usually customized for one particular architecture. This talk introduces a compiler approach, called memory coloring that we have recently developed to automatically allocating the arrays in a program to an SPM. The arrays are frequently used in embedded applications such as image processing and signal processing. The novelty of this approach lies in partitioning an SPM into a pseudo register file, splitting the live ranges of arrays to create potential data transfer statements between the SPM and of-chip main memory, and finally, adapting an existing graph-colouring algorithm for register allocation to assign the arrays in the program into the register file. This compiler-directed approach is efficient due to the practical efficiency of graph-colouring algorithms. We have implemented this work in the SUIF/mach SUIF compiler framework. Preliminary results over benchmarks show that this compiler

关键词： Storage allocation (computer)

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