Although many programming languages contain exception handling mechanisms, their formal treatment - necessary for rigorous development - can be complex. Nevertheless, this paper presents a simple incorporation of exit...
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As information systems become more complex, formal methods offer a solution to the increasing problem of ensuring correctness of design and implementation. This paper illustrates the use of mathematical specification ...
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This paper generalizes an algebraic method for the design of a correct compiler to tackle specification and verification of an optimized compiler. The main optimization issues of concern here include the use of existi...
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In this paper, the Z notation is used to develop a small theory of terms and substitutions within which a simple unification algorithm can be specified and proved correct. Particular emphasis is placed on the use of Z...
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In this paper we deal with the problem of (nondeterministic and parallel) process refinement. The basic notion of refinement is defined via the improved failure semantics of CSP [BHR84, BrR85, Hoa85, Ros88]. The conce...
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Machines have proved very successful in the implementation of very high level logic and functional programming languages;in particular, we have the G-machine for functional programming languages and the WAM for Prolog...
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The authors describe a method for speeding up divide-and-conquer algorithms with a hardware coprocessor, using sorting as an example. The method employs a conventional processor for the 'divide' and 'merge...
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A scheme is presented which transforms systolic programs with a two-dimensional structure to one dimension. The elementary steps of the transformation are justified by theorems in the theory of communicating sequentia...
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The study of computing is split at an early stage between the separate branches that deal with hardware and software; there is also a corresponding split in later professional specialisation. This paper explores the e...
The study of computing is split at an early stage between the separate branches that deal with hardware and software; there is also a corresponding split in later professional specialisation. This paper explores the essential unity of the two branches and attempts to point to a common framework within which hardware-software codesigns can be expressed as a single executable specification, reasoned about, and transformed into implementations. We also describe a hardware/software co-design environment which has been built, and we show how designs can be realised within this environment. A rapid development cycle is achieved by using FPGAs to host the hardware components of the system. The achitecture of a hardware platform for supporting experimental hardware/software co-designs is presented. A particular example of a real-time processing application built using this design environment is also described.
All the parallel discrete event simulation algorithms developed so far have been designed to suit a specific parallel model (e.g., a PRAM model, a MP-RAM model, etc.). This paper presents several versions of conservat...
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All the parallel discrete event simulation algorithms developed so far have been designed to suit a specific parallel model (e.g., a PRAM model, a MP-RAM model, etc.). This paper presents several versions of conservative parallel discrete event simulation algorithms developed around a unifying model for general purpose parallel computer design and programming, namely around the Bulk Synchronous Parallel (BSP) model. The new algorithms are analysed in terms of the BSP model parameters and the effectiveness of simulators based on these algorithms is evaluated. The performance achieved even for a loosely coupled distributed system is comparable with that reported in previous research work, while the generality of the BSP model provides portability to the new approaches.
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