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Code sharing among states for stack-caching interpreter 04

Code sharing among states for stack-caching interpreter

引用

2nd Workshop on Interpreters, Virtual Machines and Emulators, IVME 2004

作者： Jinzhan, Peng Gansha, Wu Guei-Yuan, Lueh Programming System Lab Intel Corporation China

ISBN: (纸本)1581139098

Interpretation has salient merits of simplicity, portability and small footprint but comes with a price of poor performance. Stack caching is a technique to build a high-performance interpreter by keeping source and destination operands of instructions in registers so as to reduce memory accesses involved during interpretation. One drawback of stack caching is that an instruction may have multiple ways to perform interpretation depending on which registers source operands reside in, resulting in code explosion as well as deterioration of code maintainability. This paper presents a code sharing mechanism that achieves performance as efficient as the stack-caching interpreter and in the meantime keeps the code size as compact as general threaded interpreters. Our results show that our approach outperforms a threaded interpreter by an average of 13.6% and the code size increases by only 1KB (∼3%). Copyright 2004 ACM.

关键词： Virtual machine

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Rapidly prototyping implementation infrastructure of Domain Specific Languages: A semantics-based approach

Rapidly prototyping implementation infrastructure of Domain ...

引用

20th Annual ACM Symposium on Applied Computing

作者： Wang, Qian Gupta, Gopal Applied Logic Programming-Languages and System Lab Department of Computer Science University of Texas Dallas

Domain Specific Languages (DSLs) are high level languages designed for solving problems in a particular domain, and have been suggested as means for developing reliable software systems. However, designing of a domain specific language is a difficult task. The design of a domain specific language will evolve as it is used more and more and experienced is gained by its designers. Being able to rapidly develop the implementation infrastructure (interpreter, compiler, debugger, profiler, etc.) of a domain specific language is thus of utmost importance so that as the language evolves, the implementation infrastructure can keep pace. In this paper we present a framework for automatically generating interpreters, compilers, debuggers, and profilers from semantic specification of a domain specific language. We illustrate our approach via the SCR language, a language used by the US defense department for developing control systems. Copyright 2005 ACM.

关键词： Software prototyping

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McRT-malloc - A scalable transactional memory allocator 06

McRT-malloc - A scalable transactional memory allocator

引用

ISMM 2006 - 2006 International Symposium on Memory Management

作者： Hudson, Richard L. Saha, Bratin Adl-Tabatabai, Ali-Reza Hertzberg, Benjamin C. Programming System Lab Microprocessor Technology Lab Intel Corporation Computer Architecture Lab Stanford University Palo Alto CA

ISBN: (纸本)1595932216

Emerging multi-core processors promise to provide an exponentially increasing number of hardware threads with every generation. Applications will need to be highly concurrent to fully use the power of these processors. To enable maximum concurrency, libraries (such as malloc-free packages) would therefore need to use non-blocking algorithms. But lock-free algorithms are notoriously difficult to reason about and inappropriate for average programmers. Transactional memory promises to significantly ease concurrent programming for the average programmer. This paper describes a highly efficient non-blocking malloc/free algorithm that supports memory allocation and deallocation inside transactional code blocks. Thus this paper describes a memory allocator 1 that is suitable for emerging multicore applications, while supporting modem concurrency constructs. This paper makes several novel contributions. It is the first to integrate a software transactional memory system with a malloc/free based memory allocator. We present the first algorithm which ensures that space allocated in an aborted transaction is properly freed and does not lead to a space blowup. Unlike previous lock-free malloc packages, our algorithm avoids atomic operations on typical code paths, making our algorithm substantially more efficient. Copyright © 2006 ACM.

关键词： Storage allocation (computer)

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McRT-STM: A high performance software transactional memory system for a multi-core runtime

McRT-STM: A high performance software transactional memory s...

引用

2006 ACM SIGPLAN Symposium on Principles and Practice of Parallel programming, PPOPP'06

作者： Saha, Bratin Adl-Tabatabai, Ali-Reza Hudson, Richard L. Chi, Cao Minh Hertzberg, Benjamin Programming System Lab. Microprocessor Technology Lab. Intel Corporation Computer Architecture Lab. Stanford University Palo Alto CA

ISBN: (纸本)1595931899

Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed this concurrency using locks (mutex based synchronization). Unfortunately, lock based synchronization often leads to deadlocks, makes fine-grained synchronization difficult, hinders composition of atomic primitives, and provides no support for error recovery. Transactions avoid many of these problems, and therefore, promise to ease concurrent programming. We describe a software transactional memory (STM) system that is part of McRT, an experimental Multi-Core RunTime. The McRT-STM implementation uses a number of novel algorithms, and supports advanced features such as nested transactions with partial aborts, conditional signaling within a transaction, and object based conflict detection for C/C++ applications. The McRT-STM exports interfaces that can be used from C/C++ programs directly or as a target for compilers translating higher level linguistic constructs. We present a detailed performance analysis of various STM design tradeoffs such as pessimistic versus optimistic concurrency, undo logging versus write buffering, and cache line based versus object based conflict detection. We also show a MCAS implementation that works on arbitrary values, coexists with the STM, and can be used as a more efficient form of transactional memory. To provide a baseline we compare the performance of the STM with that of fine-grained and coarse-grained locking using a number of concurrent data structures on a 16-processor SMP system. We also show our STM performance on a non-synthetic workload - the Linux sendmail application. Copyright © 2006 ACM.

关键词： Data storage equipment

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Recipient suggestion for electronic messages using local social network data 10

Recipient suggestion for electronic messages using local soc...

引用

10th Spring Researchers Colloquium on Databases and Information systems, SYRCoDIS 2014

作者： Gomzin, Andrey Ipatov, Stepan Korshunov, Anton Kim, Hangkyu Institute for System Programming of Russian Academy of Sciences Data Intellegence Lab. DMC R and D Center Russia

Social network users often want to send a message to a group of recipients. An algorithm that recommends other possible recipients given an initial set of recipients is introduced in this paper. The algorithm uses different types of local user data: profile, friendship graph, posts, and social interactions (likes, comments, tags). Experimental evaluation using Facebook application demonstrated that the algorithm is able to make suggestions meaningful to experts.

关键词： User profile

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Clustering-based microcode compression

Clustering-based microcode compression

引用

24th International Conference on Computer Design 2006, ICCD

作者： Borin, Edson Breternitz Jr., Mauricio Youfeg, Wu Araujo, Guido Institute of Computing University of Campinas Campinas SP Brazil Programming System Lab. Intel Corporation Santa Clara CA United States

Microcode enables programmability of (micro) architectural structures to enhance functionality and to apply patches to an existing design. As more features get added to a CPU core, the area and power costs associated with microcode increase. A recent Intel internal design targeted at low power and small footprint has estimated the costs of the microcode ROM to approach 20% of the total die area (and associated power consumption). Therefore, it is desirable to apply compression techniques to microcode. Microcode poses unique challenges for compression due to the long instruction format, the hand-coded nature of the programs and the stringent performance requirements that require fast decompression. This paper describes techniques for microcode compression that achieve significant area and power savings, while presenting a streamlined architecture that enables high throughput within the constraints of a high performance CPU. The paper presents results for microcode compression on several commercial CPU designs which demonstrates compression ratios ranging from 50% to 62%. © 2006 IEEE.

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Searching by Code: a New SearchBySnippet Dataset and SnippeR Retrieval Model for Searching by Code Snippets 30

Searching by Code: a New SearchBySnippet Dataset and SnippeR...

引用

Joint 30th International Conference on Computational Linguistics and 14th International Conference on Language Resources and Evaluation, LREC-COLING 2024

作者： Sedykh, Ivan Abulkhanov, Dmitry Sorokin, Nikita Nikolenko, Sergey Malykh, Valentin Huawei Noah's Ark Lab Canada St. Petersburg Department The Steklov Institute of Mathematics Russia Ivannikov Institute for System Programming Russia

ISBN: (纸本)9782493814104

Code search is an important and well-studied task, but it usually means searching for code by a text query. We argue that using a code snippet (and possibly an error traceback) as a query while looking for bugfixing instructions and code samples is a natural use case not covered by prior art. Moreover, existing datasets use code comments rather than full-text descriptions as text, making them unsuitable for this use case. We present a new SearchBySnippet dataset implementing the search-by-code use case based on StackOverflow data;we show that on SearchBySnippet, existing architectures fall short of a simple BM25 baseline even after fine-tuning. We present a new single encoder model SnippeR that outperforms several strong baselines on SearchBySnippet with a result of 0.451 Recall@10;we propose the SearchBySnippet dataset and SnippeR as a new important benchmark for code search evaluation. © 2024 ELRA Language Resource Association: CC BY-NC 4.0.

关键词： Information retrieval

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A lock-free cache-friendly software queue buffer for decoupled software pipelining

A lock-free cache-friendly software queue buffer for decoupl...

引用

2010 International Computer Symposium, ICS 2010

作者： Chen, Wen Ren Yang, Wuu Hsu, Wei Chung Programming Language and System Lab Institute of Computer Science and Engineering National Chiao Tung University Hsinchu 30013 Taiwan System Lab. Institute of Computer Science and Engineering National Chiao Tung University Hsinchu 30013 Taiwan

ISBN: (纸本)9781424476404

Multicore has become a trend on server and client computers in recent years. Parallelization is one way to fully utilize the computing power provided by multicore architectures. Most applications of interest have complex data and control dependency, which make traditional parallelization techniques, such as DOALL and DOACROSS, inapplicable. Decoupled Software Pipelining (DSWP), a new parallelization technique, shows its potential on parallelizing general applications. However, its success relies on fast inter-core synchronization and communication. On commodity multicore platforms, the performance of current DSWP disappoints us since the overhead involving lock-based, cache dishonored software approach offsets the benefit from DSWP. We present a lock-free, cache-friendly software queue designed for DSWP. A lock-free, cache-friendly solution need take two different aspects of memory system, memory coherence and memory consistency, into *** show how inattention to these two aspects leads to incorrect or inefficient solutions. We also present our approach to providing a correct and efficient solution with detailed explanation. Due to the nondeterministic nature of parallel programs, traditional testing techniques cannot be used to fully verify the correctness of the implementation. We also discuss the correctness of our implementation both in informal and formal ways. ©2010 IEEE.

关键词： Locks (fasteners)

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Role modelling in SelfSync with warped hierarchies

Role modelling in SelfSync with warped hierarchies

引用

2005 AAAI Fall Symposium

作者： Van Paesschen, Ellen De Meuter, Wolfgang D'Hondt, Maja Programming Technology Lab. Vrije Universiteit Brussel Pleinlaan 2 1050 Brussel System Software Engineering Lab. Vrije Universiteit Brussel Pleinlaan 2 1050 Brussel

ISBN: (纸本)1577352548

In object-oriented software engineering roles are considered both classifications and instances. To reduce the gap between the conceptual modelling of roles and a corresponding implementation, we propose a new role modelling concept based on warped inheritance hierarchies. We integrated this new modelling concept in our prototype-based object-oriented round-trip engineering environment SelfSync. In this way it is possible to model roles in an Extended Entity-Relationship diagram while the corresponding implementation objects are automatically created and synchronized with the conceptual model. We apply constraint enforcement during the lifetime of role objects, based on dependency and role combinations. Copyright © 2005, American Association for Artificial Intelligence (***). All rights reserved.

关键词： Software engineering

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DEUCE: Separating concerns in user interfaces

DEUCE: Separating concerns in user interfaces

引用

2nd International Conference on Software Engineering Advances - ICSEA 2007

作者： Goderis, Sofie Deridder, Dirk Van Paesschen, Ellen Programming Technology Lab. Vrije Universiteit Brussel System and Software Engineering Lab. Vrije Universiteit Brussel Laboratoire d'Informatique Fondamentale de Lille University of Lille 1

ISBN: (纸本)0769529372

As current software systems evolve continuously, both the application and its user interface (UI) have to be adapted. However, UI code is often scattered through and entangled with the application code. In large and complex UIs, this tangling renders the implementation complex and hard to maintain. The Deuce framework (Declarative User Interface Concerns Extrication) intends to reduce the complexity of UI implementations by applying separation of concerns on three UI concerns: presentation logic, business and data logic, and connection logic. It does so by using a declarative meta-language (SOUL) on top of an object oriented language (Smalltalk) such that an adequate language is provided to describe the entire structure and behavior of the UI, as well as linking it with the application. © 2007 IEEE.

关键词： User interfaces

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