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2006 ACM SIGPLAN Symposium on Principles and Practice of Parallel programming, PPOPP'06

作者： Saha, Bratin Adl-Tabatabai, Ali-Reza Hudson, Richard L. Chi, Cao Minh Hertzberg, Benjamin Programming System Lab. Microprocessor Technology Lab. Intel Corporation Computer Architecture Lab. Stanford University Palo Alto CA

ISBN: (纸本)1595931899

Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed this concurrency using locks (mutex based synchronization). Unfortunately, lock based synchronization often leads to deadlocks, makes fine-grained synchronization difficult, hinders composition of atomic primitives, and provides no support for error recovery. Transactions avoid many of these problems, and therefore, promise to ease concurrent programming. We describe a software transactional memory (STM) system that is part of McRT, an experimental Multi-Core RunTime. The McRT-STM implementation uses a number of novel algorithms, and supports advanced features such as nested transactions with partial aborts, conditional signaling within a transaction, and object based conflict detection for C/C++ applications. The McRT-STM exports interfaces that can be used from C/C++ programs directly or as a target for compilers translating higher level linguistic constructs. We present a detailed performance analysis of various STM design tradeoffs such as pessimistic versus optimistic concurrency, undo logging versus write buffering, and cache line based versus object based conflict detection. We also show a MCAS implementation that works on arbitrary values, coexists with the STM, and can be used as a more efficient form of transactional memory. To provide a baseline we compare the performance of the STM with that of fine-grained and coarse-grained locking using a number of concurrent data structures on a 16-processor SMP system. We also show our STM performance on a non-synthetic workload - the Linux sendmail application. Copyright © 2006 ACM.

关键词： Data storage equipment

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Recipient suggestion for electronic messages using local social network data 10

Recipient suggestion for electronic messages using local soc...

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10th Spring Researchers Colloquium on Databases and Information systems, SYRCoDIS 2014

作者： Gomzin, Andrey Ipatov, Stepan Korshunov, Anton Kim, Hangkyu Institute for System Programming of Russian Academy of Sciences Data Intellegence Lab. DMC R and D Center Russia

Social network users often want to send a message to a group of recipients. An algorithm that recommends other possible recipients given an initial set of recipients is introduced in this paper. The algorithm uses different types of local user data: profile, friendship graph, posts, and social interactions (likes, comments, tags). Experimental evaluation using Facebook application demonstrated that the algorithm is able to make suggestions meaningful to experts.

关键词： User profile

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Role modelling in SelfSync with warped hierarchies

Role modelling in SelfSync with warped hierarchies

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2005 AAAI Fall Symposium

作者： Van Paesschen, Ellen De Meuter, Wolfgang D'Hondt, Maja Programming Technology Lab. Vrije Universiteit Brussel Pleinlaan 2 1050 Brussel System Software Engineering Lab. Vrije Universiteit Brussel Pleinlaan 2 1050 Brussel

ISBN: (纸本)1577352548

In object-oriented software engineering roles are considered both classifications and instances. To reduce the gap between the conceptual modelling of roles and a corresponding implementation, we propose a new role modelling concept based on warped inheritance hierarchies. We integrated this new modelling concept in our prototype-based object-oriented round-trip engineering environment SelfSync. In this way it is possible to model roles in an Extended Entity-Relationship diagram while the corresponding implementation objects are automatically created and synchronized with the conceptual model. We apply constraint enforcement during the lifetime of role objects, based on dependency and role combinations. Copyright © 2005, American Association for Artificial Intelligence (***). All rights reserved.

关键词： Software engineering

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DEUCE: Separating concerns in user interfaces

DEUCE: Separating concerns in user interfaces

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2nd International Conference on Software Engineering Advances - ICSEA 2007

作者： Goderis, Sofie Deridder, Dirk Van Paesschen, Ellen Programming Technology Lab. Vrije Universiteit Brussel System and Software Engineering Lab. Vrije Universiteit Brussel Laboratoire d'Informatique Fondamentale de Lille University of Lille 1

ISBN: (纸本)0769529372

As current software systems evolve continuously, both the application and its user interface (UI) have to be adapted. However, UI code is often scattered through and entangled with the application code. In large and complex UIs, this tangling renders the implementation complex and hard to maintain. The Deuce framework (Declarative User Interface Concerns Extrication) intends to reduce the complexity of UI implementations by applying separation of concerns on three UI concerns: presentation logic, business and data logic, and connection logic. It does so by using a declarative meta-language (SOUL) on top of an object oriented language (Smalltalk) such that an adequate language is provided to describe the entire structure and behavior of the UI, as well as linking it with the application. © 2007 IEEE.

关键词： User interfaces

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Clustering-based microcode compression

Clustering-based microcode compression

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24th International Conference on Computer Design 2006, ICCD

作者： Borin, Edson Breternitz Jr., Mauricio Youfeg, Wu Araujo, Guido Institute of Computing University of Campinas Campinas SP Brazil Programming System Lab. Intel Corporation Santa Clara CA United States

Microcode enables programmability of (micro) architectural structures to enhance functionality and to apply patches to an existing design. As more features get added to a CPU core, the area and power costs associated with microcode increase. A recent Intel internal design targeted at low power and small footprint has estimated the costs of the microcode ROM to approach 20% of the total die area (and associated power consumption). Therefore, it is desirable to apply compression techniques to microcode. Microcode poses unique challenges for compression due to the long instruction format, the hand-coded nature of the programs and the stringent performance requirements that require fast decompression. This paper describes techniques for microcode compression that achieve significant area and power savings, while presenting a streamlined architecture that enables high throughput within the constraints of a high performance CPU. The paper presents results for microcode compression on several commercial CPU designs which demonstrates compression ratios ranging from 50% to 62%. © 2006 IEEE.

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A lock-free cache-friendly software queue buffer for decoupled software pipelining

A lock-free cache-friendly software queue buffer for decoupl...

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2010 International Computer Symposium, ICS 2010

作者： Chen, Wen Ren Yang, Wuu Hsu, Wei Chung Programming Language and System Lab Institute of Computer Science and Engineering National Chiao Tung University Hsinchu 30013 Taiwan System Lab. Institute of Computer Science and Engineering National Chiao Tung University Hsinchu 30013 Taiwan

ISBN: (纸本)9781424476404

Multicore has become a trend on server and client computers in recent years. Parallelization is one way to fully utilize the computing power provided by multicore architectures. Most applications of interest have complex data and control dependency, which make traditional parallelization techniques, such as DOALL and DOACROSS, inapplicable. Decoupled Software Pipelining (DSWP), a new parallelization technique, shows its potential on parallelizing general applications. However, its success relies on fast inter-core synchronization and communication. On commodity multicore platforms, the performance of current DSWP disappoints us since the overhead involving lock-based, cache dishonored software approach offsets the benefit from DSWP. We present a lock-free, cache-friendly software queue designed for DSWP. A lock-free, cache-friendly solution need take two different aspects of memory system, memory coherence and memory consistency, into *** show how inattention to these two aspects leads to incorrect or inefficient solutions. We also present our approach to providing a correct and efficient solution with detailed explanation. Due to the nondeterministic nature of parallel programs, traditional testing techniques cannot be used to fully verify the correctness of the implementation. We also discuss the correctness of our implementation both in informal and formal ways. ©2010 IEEE.

关键词： Locks (fasteners)

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Seamless integration of rule-based knowledge and object-oriented functionality with linguistic symbiosis 04

Seamless integration of rule-based knowledge and object-orie...

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Applied Computing 2004 - Proceedings of the 2004 ACM Symposium on Applied Computing

作者： D'Hondt, Maja Gybels, Kris Jonckers, Viviane System and Software Engineering Lab. Vrije Universiteit Brussel Belgium Programming Technology Lab. Vrije Universiteit Brussel Belgium Flemish Inst. Prom. Sci.-T.R.I. Flanders Belgium Fund for Scientific Research Flanders Belgium

ISBN: (纸本)9781581138122

Software applications often contain implicit knowledge in addition to functionality which is inherently object-oriented. Many approaches and systems exist that focus on separating rule-based knowledge from object-oriented functionality and representing it explicitly in a logic reasoning system. Support for seamless integration of this knowledge with the object-oriented functionality improves software development and evolution. Our hypothesis is that a linguistic symbiosis is required between the logic reasoning and object-oriented programming paradigms in order to achieve seamless integration. This paper presents a symbiotic extension of SOUL, a system which implements a logic programming language and a production system in Smalltalk. The presence of these two logic reasoning systems in SOUL ensures a comprehensive coverage of rule-based reasoning styles, more specifically forward and backward chaining. Our approach is evaluated by means of two case studies. We summarise a comprehensive survey, which shows that existing systems do not fully support seamless integration.

关键词： Object oriented programming

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pioNER: Datasets and Baselines for Armenian Named Entity Recognition

pioNER: Datasets and Baselines for Armenian Named Entity Rec...

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Ivannikov ISPRAS Open Conference (ISPRAS)

作者： Tsolak Ghukasyan Garnik Davtyan Karen Avetisyan Ivan Andrianov Ivannikov Laboratory for System Programming at Russian Armenian University Yerevan Armenia Ivannikov Lab. for Syst. Program. Russian-Armenian Univ. Moscow Russia Ivannikov Institute for System Programming of the Russian Academy of Sciences Moscow Russia

ISBN: (纸本)9781728112763;9781728112756

In this work, we tackle the problem of Armenian named entity recognition, providing silverand gold-standard datasets as well as establishing baseline results on popular models. We present a 163000-token named entity corpus automatically generated and annotated from Wikipedia, and another 53400token corpus of news sentences with manual annotation of people, organization and location named entities. The corpora were used to train and evaluate several popular named entity recognition models. Alongside the datasets, we release 50-, 100-, 200-, 300dimensional GloVe word embeddings trained on a collection of Armenian texts from Wikipedia, news, blogs, and encyclopedia.

关键词： Encyclopedias Electronic publishing Internet Organizations Standards organizations Sports

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From fault tolerance to security and back

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IEEE Distributed systems Online 2003年第9期4卷

作者： Gartner, Felix C. Buttyan, Levente Kursawe, Klaus Swiss Fed. Institute of Technology Switzerland Budapest Univ. of Technol./Economics Hungary IBM Research Distributed Programming Laboratory Swiss Fed. Institute of Technology Lausanne Switzerland Lab. of Cryptography/System Security Budapest Univ. of Technol./Economics Hungary Department of Computer Switzerland

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