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MICRO-38: 38th Annual IEEE/ACM International Symposium on Microarchitecture

作者： Wu, Qiang Reddi, V.J. Wu, Youfeng Lee, Jin Connors, Dan Brooks, David Martonosi, Margaret Clark, Douglas W. Depts. of Computer Science Electrical Engjneering Princeton University Dept. of Electrical and Computer Engineering U. of Colorado Boulder Programming Systems Lab. Corporate Tech. Group Intel Corporation Division of Engineering and Applied Science Harvard University

ISBN: (纸本)0769524400

Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS timeinterrupts, or static-compiler techniques. However, substantially greater gains can be realized when control opportunities are also explored in a dynamic compilation environment. There are several advantages to deploying DVFS and managing energy/performance tradeoffs through the use of a dynamic compiler. Most importantly, dynamic compiler driven DVFS is fine-grained, code-aware, and adaptive to the current microarchitecture environment. This paper presents a design framework of the run-time DVFS optimizer in a general dynamic compilation system. A prototype of the DVFS optimizer is implemented and integrated into an industrialstrength dynamic compilation system. The obtained optimization system is deployed in a real hardware platform that directly measures CPU voltage and current for accurate power and energy readings. Experimental results, based on physical measurements for over 40 SPEC or Olden benchmarks, show that significant energy savings are achieved with little performance degradation. SPEC2K FP benchmarks benefit with energy savings of up to 70% (with 0.5% performance loss). In addition, SPEC2K INT show up to 44% energy savings (with 5% performance loss), SPEC95 FP save up to 64% (with 4.9% performance loss), and Olden save up to 61% (with 4.5% performance loss). On average, the technique leads to an energy delay product (EDP) improvement that is 3X-5X better than static voltage scaling, and is more than 2X (22% vs. 9%) better than the reported DVFS results of prior static compiler work. While the proposed technique is an effective method for microprocessor voltage and frequency control, the design framework and methodology described in this paper have broader potential to address other energy and power issues such as di/dt and thermal control. © 2005 IEEE.

关键词： Microprocessor chips

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The use of a Reasoning process to solve the almost SLAM Challenge at the Robocup legged league

The use of a Reasoning process to solve the almost SLAM Chal...

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8th Catalan Conference on Artificial Intelligence, CCIA 2005

作者： Monferrer, M. Teresa Escrig Broch, Juan Carlos Peris Jaume I University Engineering and Computer Science Department Campus Riu Sec CastellónE-12071 Spain Jaume I University Programming Languages and Computer Systems Department Campus Riu Sec CastellónE-12071 Spain

ISBN: (纸本)1586035606

The problem that a robot navigates autonomously through its environment, builds its own map and localizes itself in the map (known a the SLAM problem), is still an open problem. Most of the approaches to solve the SLAM problem divide the space into regions and compute the probability that the robot is in each region. We propose in this paper a different solution based on the use of a reasoning process to build the map, which will provide the following advantages: (1) we will store in the map hybrid (qualitative + quantitative) information from landmarks. Qualitative representation will allow us the management of the uncertainty information provided by the robot sensors;and (2) we will store in the map relative information of the landmarks which appear in the environment, therefore the map will be independent of the point of view of the robot. Moreover, we are going to use a reasoning process which will allow us to solve three very important problems in robotics: (a) where the robot is;(b) which is the orientation of the map where the robot is;and (c) towards where the robot should go according to the map to follow a plan. © 2005 The authors. All rights reserved.

关键词： Robots

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A Formal Model of XML Schema

A Formal Model of XML Schema

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International Conference on Data Engineering Workshops

作者： L. Novak A. Zamulin Institute for System Programming Russian Academy of Science Moscow Russia A.P. Ershov Institute of Informatics Systems Russian Academy of Science Novosibirsk Russia

The semantics of the core features of XML Schema in terms of XQuery 1.0 and XPath 2.0 data model algebraically defined is given. The database state is represented as a many sorted algebra whose sorts are sets of data type values and different kinds of nodes and whose operations are data type operations and node accessors. The values of some node accessors, such as "parent", "children" and "attributes", define a document tree with a definite order of nodes. The values of other node accessors help to make difference between kinds of nodes, learn the names, types and values associated with the corresponding document entities, etc., i.e., provide primitive facilities for a query language. As a result, a document can be easily mapped to its implementation in terms of nodes and accessors defined on them.

关键词： XML Data models Algebra Database languages Informatics Spatial databases Data engineering

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Autonomous applications - Towards a better data integration model

Autonomous applications - Towards a better data integration ...

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9th East-European Conference on Advances in Databases and Information systems, ADBIS 2005

作者： Benczúr, András Hernáth, Zsolt Porkoláb, Zoltán Eötvös Loránd University Faculty of Informatics Dept. of Information Systems Pazmany Peter setany 1/C H-1117 Budapest Hungary Eötvös Loránd University Faculty of Informatics Dept. of Programming Languages and Compilers Pazmany Peter setany 1/C H-1117 Budapest Hungary

One of the most important and critical part of integrating already existing standalone applications is to design and implement a common data model and the corresponding data access layer which makes both data sources and processed results being shared and accessible over the applications in question. In case of even well-architected applications or application systems, establishing a common data model and the layer that gives access to data costs relatively large human and computer development resources. The problem of integration may be investigated from several aspects. The esence of these aproaches are the same: trying to achieve run-time environment independent applications' logic. One aspect is OMG's Model Driven Architecture Frame Work [5]. The primary goals of OMG's MDA are portability, interoperability and resuability through architectural concernes of specifying Application's logic, their operational environments, and technical aspects of their implementation details, and mappings between them. This paper views the same problem but with focus on different structural apearances of applications' data, mappings between them, and possible integration of such data models. We call applications autonomous, if they are independent of their all time run-time data access environment. Concerning applications' autonomy, our base idea is that the most natural media that is able to carry information on structural apperance of data and mappings between them are data themselves, using Document Data Model also presented here.

关键词： Mapping

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Characterization and analysis of HMMER and SVM-RFE parallel bioinformatics applications

Characterization and analysis of HMMER and SVM-RFE parallel ...

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IEEE International Workshop/Symposium on Workload Characterization

作者： U. Srinivasan Peng-Sheng Chen Qian Diao Chu-Cheow Lim E. Li Yongjian Chen R. Ju Yimin Zhang Programming Systems Laboratoryoratory Microprocessor Technology Laboratory Intel Corporation Santa Clara CA USA Architecture Research Laboratoryoratory Microprocessor Technology Laboratory Intel Corporation Santa Clara CA USA

Bioinformatics applications constitute an emerging data-intensive, high-performance computing (HPC) domain. While there is much research on algorithmic improvements, (2004), the actual performance of an application also depends on how well the program maps to the target hardware. This paper presents a performance study of two parallel bioinformatics applications HMMER (sequence alignment) and SVM-RFE (gene expression analysis), on Intel x86 based hyperthread-capable (2002) shared-memory multiprocessor systems. The performance characteristics varied according to the application and target hardware characteristics. For instance, HMMER is compute intensive and showed better scalability on a 3.0 GHz system versus a 2.2 GHz system. However, SVM-RFE is memory intensive and showed better absolute performance on the 2.2 GHz machine which has better memory bandwidth. The performance is also impacted by processor features, e.g. hyperthreading (HT) (2002) and prefetching. With HMMER we could obtain -75% of the performance with HT enabled with respect to doubling the number of CPUs. While load balancing optimizations can provide speedup of -30% for HMMER on a hyperthreading-enabled system, the load balancing has to adapt to the target number of processors and threads. SVM-RFE benefits differently from the same load-balancing and thread scheduling tuning. We conclude that compiler and runtime optimizations play an important role to achieve the best performance for a given bioinformatics algorithm.

关键词： Hidden Markov models Bioinformatics Hardware Load management Yarn Gene expression Performance analysis Multiprocessing systems Scalability Bandwidth

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Enhanced code density of embedded CISC processors with Echo technology 05

Enhanced code density of embedded CISC processors with Echo ...

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3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and systems Synthesis CODES+ISSS 2005

作者： Wu, Youfeng Breternitz Jr., Mauricio Hum, Herbert Peri, Ramesh Pickett, Jay Programming Systems Lab. Intel Labs. 2200 Mission College Blvd Santa Clara CA 95054 United States Low Power Microprocessor Lab. Intel Labs. 2200 Mission College Blvd Santa Clara CA 95054 United States Compiler Lab. Intel Labs. 2200 Mission College Blvd Santa Clara CA 95054 United States

ISBN: (纸本)1595931619

Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even at the cost of significant performance loss. In this paper, we develop an algorithm that utilizes a set of novel variable length Echo instructions and evaluate its effectiveness for IA32 binaries. Our experiments show that IA32 processor equipped with Echo instructions is capable of achieving a similar code density as the THUMB extension in the ARM instruction set with significantly lower performance penalty. Copyright 2005 ACM.

关键词： Microprocessor chips

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A dynamic compilation framework for controlling microprocessor energy and performance

A dynamic compilation framework for controlling microprocess...

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IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： Qiang Wu V.J. Reddi Youfeng Wu Jin Lee D. Connors D. Brooks M. Martonosi D.W. Clark Depts. of Computer Science Electrical Engineering Princeton University USA Department of Electrical and Computer Engineering University of Colorado Boulder USA Programming Systems Laboratory Intel Corporation USA Division of Engineering and Applied Science Harvard University USA

Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS time-interrupts, or static-compiler techniques. However, substantially greater gains can be realized when control opportunities are also explored in a dynamic compilation environment. There are several advantages to deploying DVFS and managing energy/performance tradeoffs through the use of a dynamic compiler. Most importantly, dynamic compiler driven DVFS is fine-grained, code-aware, and adaptive to the current microarchitecture environment. This paper presents a design framework of the run-time DVFS optimizer in a general dynamic compilation system. A prototype of the DVFS optimizer is implemented and integrated into an industrial-strength dynamic compilation system. The obtained optimization system is deployed in a real hardware platform that directly measures CPU voltage and current for accurate power and energy readings. Experimental results, based on physical measurements for over 40 SPEC or Olden benchmarks, show that significant energy savings are achieved with little performance degradation. SPEC2K FP benchmarks benefit with energy savings of up to 70% (with 0.5% performance loss). In addition, SPEC2K INT show up to 44% energy savings (with 5% performance loss), SPEC95 FP save up to 64% (with 4.9% performance loss), and Olden save up to 61% (with 4.5% performance loss). On average, the technique leads to an energy delay product (EDP) improvement that is 3times-5times better than static voltage scaling, and is more than 2times (22% vs. 9%) better than the reported DVFS results of prior static compiler work. While the proposed technique is an effective method for microprocessor voltage and frequency control, the design framework and methodology described in this paper have broader potential to address other energy and power issues such as di/dt and thermal control

关键词： Dynamic compiler Microprocessors Performance loss Voltage control Hardware Energy measurement Dynamic voltage scaling Frequency Energy management Microarchitecture

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Detecting and preventing programmable IC defects prior to placement

SMT Surface Mount Technology Magazine

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SMT Surface Mount Technology Magazine 2004年第1期18卷 36-38页

作者： Corken, Kevin Product Manager for Automated Programming Systems BP Microsystems

Some of the significant factors that need to be considered to detect and prevent programmable integrated circuits (IC) defects, are discussed. The failure analysis of ICs can detect the cause of failure of a board on a SMT line. An IC can be damaged by internal lot-sensitive defects and external packaging or handling defects. The internal defects need to be detected by programming before placing it on the board. Defects can caused by humidity, temperature, vibration, or any mechanical disturbances. The external forces responsible for defects are moisture penetration, mechanical stress cracks, improper bonding, crystal defects, and fabrication faults. A X-ray test can be used to detect poor bonding interfaces, wire sweep, voids in the die attach, and voids in the molding compounds. programming before placement can reduce the scrap and re-work.

关键词： Timing circuits

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Lexicalized syntax and topology for non-projective dependency grammar

Lexicalized syntax and topology for non-projective dependenc...

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Proceedings of the Joint Meeting of the 6th Conference on Formal Grammar and the 7th Conference on Mathematics of Language

作者： Duchier, Denys Programming Systems Lab Universität des Saarlandes Saarbrücken Germany

We propose a lexicalized formulation of dependency grammar that addresses both immediate dependence and linear precedence. Our approach distinguishes two orthogonal, yet mutually constraining dependency trees: an ID tree of syntactic dependencies and a LP tree of topological dependencies. The ID tree is non-ordered, non-projective and its edges are labeled by grammatical functions. The LP tree is ordered and projective and expresses licensed linearizations;its edges are labeled by topological fields. The LP tree can be regarded as deriving from the ID tree through a process of emancipation controlled by lexicalized constraints and principles. In the present article, we formalize valid ID/LP analyses and show how they can be characterized as the solutions of a constraint satisfaction problem. The latter can be solved by constraint programming and forms the basis of our implementation. © 2004 Published by Elsevier Science B.V.

关键词： Context free grammars

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Prefetch injection based on hardware monitoring and object metadata

Prefetch injection based on hardware monitoring and object m...

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Proceedings of the 2004 ACM SIGPLAN Conference on programming Language Design and Implementation (PLDI'04)

作者： Adl-Tabatabai, Ali-Reza Hudson, Richard L. Serrano, Mauricio J. Subramoney, Sreenivas Programming Systems Laboratory Microprocessor Technology Laboratory Intel Corporation Santa Clara CA United States

Cache miss stalls hurt performance because of the large gap between memory and processor speeds - for example, the popular server benchmark SPEC JBB2000 spends 45% of its cycles stalled waiting for memory requests on the Itanium® 2 processor. Traversing linked data structures causes a large portion of these stalls. Prefetching for linked data structures remains a major challenge because serial data dependencies between elements in a linked data structure preclude the timely materialization of prefetch addresses. This paper presents Mississippi Delta (MS Delta), a novel technique for prefetching linked data structures that closely integrates the hardware performance monitor (HPM), the garbage collector's global view of heap and object layout, the type-level metadata inherent in type-safe programs, and JIT compiler analysis. The garbage collector uses the HPM's data cache miss information to identify cache miss intensive traversal paths through linked data structures, and then discovers regular distances (deltas) between these linked objects. JIT compiler analysis injects prefetch instructions using deltas to materialize prefetch addresses. We have implemented MS Delta in a fully dynamic profile-guided optimization system: the StarJIT dynamic compiler and the ORP Java virtual machine, We demonstrate a 28-29% reduction in stall cycles attributable to the high-latency cache misses targeted by MS Delta and a speedup of 11-14% on the cache miss intensive SPEC JBB2000 benchmark.

关键词： Cache memory

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