A hardware/software co-designed processor transparently supports a ubiquitous ISA (e.g. x86) with diversified and innovative microarchitectural implementations. It leverages co-designed HW features and dynamic binary ...
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ISBN:
(纸本)9781467355254;9781467355247
A hardware/software co-designed processor transparently supports a ubiquitous ISA (e.g. x86) with diversified and innovative microarchitectural implementations. It leverages co-designed HW features and dynamic binary translation (DBT) SW to morph existing binary programs to scale performance and save power. On such systems, the portable bytecode of modern dynamic languages (e.g. Java, JavaScript, etc.) is first translated into the code in the architecture ISA by the just-in-time (JIT) compilation in the bytecode virtual machine, and then into the code in the internal implementation ISA by the DBT. This not only incurs the translation overheads twice, but also brings significant emulation inefficiency as the DBT does not have the high level bytecode information. In this paper, we present AccelDroid, which accelerates the Android Dalvik bytecode execution on the HW/SW co-designed processor through direct bytecode translation in the DBT. Our experiments on a HW/SW co-designed Transmeta Efficeon machine show that AccelDroid can improve performance by 78% and save energy by 40% for the CaffeineMark 3.0 benchmark suite.
Dynamic programming Languages, such as Java, JavaScr ipt, PHP, Perl, Python, Ruby, etc., are dominating languages for programming the web. HW/SW co-designed virtual machine can significantly accelerate their execution...
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ISBN:
(纸本)9781450320856
Dynamic programming Languages, such as Java, JavaScr ipt, PHP, Perl, Python, Ruby, etc., are dominating languages for programming the web. HW/SW co-designed virtual machine can significantly accelerate their executions by transparently leveraging internal HW features via an internal compiler. We also argue for a common API to interface dynamic languages with the HW/SW co-designed virtual machine, so that a single internal compiler can accelerate all major dynamic languages.
Moore's Law will continue to increase the number of transistors on die for a couple of decades, as silicon technology moves from 65nm today to 45nm, 32 nm and 22nm in the future. Since the power and thermal constr...
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Software pipelining exploits instruction-level parallelism from loops. In static compilers, it has been one of the most eficient optimizations for wide-issue architectures. How- ever, the compilation time is at least ...
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Search is essential for constraint programming. Search engines typically combine several features like state restoration for back-tracking, best solution search, parallelism, or visualization. In current implementatio...
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Today's big data challenge presses for a breakthrough in programming models. A simple programming model capable of both high productivity and high performance is desired. This paper proposes a simple solution to r...
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ISBN:
(纸本)9781450333580
Today's big data challenge presses for a breakthrough in programming models. A simple programming model capable of both high productivity and high performance is desired. This paper proposes a simple solution to realize a set of restricted yet fundamental productivity features in C-family languages, without sacrificing their efficiency. This is achieved by leveraging a productivity language runtime and compiler analyses. Programmers write a program in the familiar C/C++/ObjectiveC style, without even knowing it is a mix of productivity and efficiency code. The program evolves as both a rapid prototype and efficiency code.
Moore's Law will continue to increase the number of transistors on die for a couple of decades, as silicon technology moves from 65nm today to 45nm, 32 nm and 22nm in the future. Since power and thermal constraint...
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ISBN:
(纸本)1595936025
Moore's Law will continue to increase the number of transistors on die for a couple of decades, as silicon technology moves from 65nm today to 45nm, 32 nm and 22nm in the future. Since power and thermal constraints increase with frequency, multi-core or many-core microprocessors will be the way of the future. In the near future, hardware platforms will have sixteen or more cores on die to achieve more than one Tera Instructions Per second (TIPs) computation power. These cores will communicate each other through an on-die interconnect fabric with more than one TB/s on-die bandwidth and less than 30 cycles latency. Off-die D-cache will employ 3D stacked memory technology to tremendously increase off-die cache/memory bandwidth and reduce the latency. Fast copper flex cables will link CPU-DRAM on socket and optical silicon photonics will provide up to one Tb/s I/O bandwidth between boxes. The hardware system with TIPs of compute power operating on terabytes of data make this a ?tera-scale? platform. What are the software implications with the hardware changes from uniprocessor to tera-scale platform with many cores as "the way of the future?" It will be a great challenge for programming environments to help programmers develop concurrent code for most client software. A good concurrent programming environment should extend existing programming languages that typical programmers are familiar with, and bring benefits for concurrent programming. There are many research topics. Examples topics include flexible parallel programming models based on needs from applications, better synchronization mechanisms such as Transactional Memory to replace simple ?Thread + Lock? structure, nested data parallel language primitives with new protocols, fine-grained synchronization mechanisms with hardware support, maybe fine-grained message passing, advanced compiler optimizations for the threaded code, and software tools in the concurrent programming environment. A more interesting proble
Requirements Engineering is one of the most important phases in any product development life cycle since it is the basis for the complete software or product design and realization. Therefore in a worst case scenario ...
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Requirements Engineering is one of the most important phases in any product development life cycle since it is the basis for the complete software or product design and realization. Therefore in a worst case scenario any error within a requirement can result in a project loss. Computer support for requirement engineers is still premature as most RE applications can not cope with more sophisticated techniques like semantics, natural language processing etc. In this paper we will present the ongoing research work in semantic requirement engineering which will try to close the gap between computer understandable semantics, namely ontologies, and the natural language input of a human.
This article consists of a collection of slides from the author's conference presentation on transactional memory (TM). Some of the specific topics discussed include: an introduction to TM;TM implementation techni...
This article consists of a collection of slides from the author's conference presentation on software transactional memory (STM). Some of the specific topics discussed include: how to translate a language construc...
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