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AccelDroid: Co-designed Acceleration of Android Bytecode

AccelDroid: Co-designed Acceleration of Android Bytecode

引用

11th IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

作者： Wang, Cheng Wu, Youfeng Cintra, Marcelo Programming Systems Lab Microprocessor and Programming Research Intel Labs

ISBN: (纸本)9781467355254;9781467355247

A hardware/software co-designed processor transparently supports a ubiquitous ISA (e.g. x86) with diversified and innovative microarchitectural implementations. It leverages co-designed HW features and dynamic binary translation (DBT) SW to morph existing binary programs to scale performance and save power. On such systems, the portable bytecode of modern dynamic languages (e.g. Java, JavaScript, etc.) is first translated into the code in the architecture ISA by the just-in-time (JIT) compilation in the bytecode virtual machine, and then into the code in the internal implementation ISA by the DBT. This not only incurs the translation overheads twice, but also brings significant emulation inefficiency as the DBT does not have the high level bytecode information. In this paper, we present AccelDroid, which accelerates the Android Dalvik bytecode execution on the HW/SW co-designed processor through direct bytecode translation in the DBT. Our experiments on a HW/SW co-designed Transmeta Efficeon machine show that AccelDroid can improve performance by 78% and save energy by 40% for the CaffeineMark 3.0 benchmark suite.

关键词： Linux hardware-software codesign instruction sets program compilers virtual machines

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HW/SW Co-designed Acceleration of Dynamic Languages

HW/SW Co-designed Acceleration of Dynamic Languages

引用

14th ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded systems

作者： Wu, Youfeng Programming Systems Lab United States

ISBN: (纸本)9781450320856

Dynamic programming Languages, such as Java, JavaScr ipt, PHP, Perl, Python, Ruby, etc., are dominating languages for programming the web. HW/SW co-designed virtual machine can significantly accelerate their executions by transparently leveraging internal HW features via an internal compiler. We also argue for a common API to interface dynamic languages with the HW/SW co-designed virtual machine, so that a single internal compiler can accelerate all major dynamic languages.

关键词： Languages Measurement Performance Dynamic languages Just-in-time Compilation HW/SW Co-designed Virtual Machine Acceleration

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Parallel programming environment: A key to translating tera-scale platforms into a big success 07

Parallel programming environment: A key to translating tera-...

引用

International Symposium on Code Generation and Optimization, CGO 2007

作者： Fang, Jesse Adl-Tabatabai, Ali Intel Programming Systems Lab.

ISBN: (纸本)0769527647

Moore's Law will continue to increase the number of transistors on die for a couple of decades, as silicon technology moves from 65nm today to 45nm, 32 nm and 22nm in the future. Since the power and thermal constraints increase with frequency, multi-core or many-core will be the way of the future microprocessor. In the near future, HW platforms will have many-cores (>16 cores) on die to achieve >1 TIPs computation power, which will communicate each other through an ondie interconnect fabric with >1 TB/s on-die bandwidth and <30 cycles latency. Off-die D-cache will employ 3D stacked memory technology to tremendously increase off-die cache/memory bandwidth and reduce the latency. Fast copper flex cables will link CPU-DRAM on socket and the optical silicon photonics will provide up to 1 Tb/s I/O bandwidth between boxes. The HW system with TIPs of compute power operating in Tera-bytes of data make this a "Tera-scale" platform. What are the SW implications with the HW changes from uniprocessor to Tera-scale platform with many-cores as "the way of the future?" It will be great challenge for programming environments to help programmers to develop concurrent code for most client software. A good concurrent programming environment should extend the existing programming languages that typical programmers are familiar with, and bring benefits for concurrent programming. There are lots of research topics. Examples of these topics include flexible parallel programming models based on needs from applications, better synchronization mechanisms like Transactional Memory to replace simple "Thread + Lock" structure, nested data parallel language primitives with new protocols, fine-grained synchronization mechanisms with HW support, maybe fine-grained message passing, advanced compiler optimizations for the threaded code, and SW tools in the concurrent programming environment. A more interesting problem is how to use such a many-core system to improve single-threaded performance. ©200

关键词： Parallel programming

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Just-in-time software pipelining

Just-in-time software pipelining

引用

12th ACM/IEEE International Symposium on Code Generation and Optimization, CGO 2014

作者： Rong, Hongbo Park, Hyunchul Wu, Youfeng Wang, Cheng Programming Systems Lab United States

ISBN: (纸本)9781450326704

Software pipelining exploits instruction-level parallelism from loops. In static compilers, it has been one of the most eficient optimizations for wide-issue architectures. How- ever, the compilation time is at least O(/V/ 3) (V : The set of operations in a loop) and in the worst-case exponential. This paper extends software pipelining to dynamic compil- ers. We present a novel and simple algorithm with linear time O(/V/ + /E/) (E: The set of edges in the dependence graph of a loop). Preliminary experiments show the method is light-weight and generates optimal or near-optimal sched- ules. Copyright © 2014 by the Association for Computing Machinery, Inc. (ACM).

关键词： Program compilers

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Compositional abstractions for search factories

Compositional abstractions for search factories

引用

Second International Conference - Multiparadigm programming in Mozart/OZ, MOZ 2004

作者： Tack, Guido Botlan, Didier Le Programming Systems Lab Saarland University Germany

Search is essential for constraint programming. Search engines typically combine several features like state restoration for back-tracking, best solution search, parallelism, or visualization. In current implementations like Mozart, however, these search engines are monolithic and hard-wired to one exploration strategy, severely complicating the implementation of new exploration strategies and preventing their reuse. This paper presents the design of a search factory for Mozart, a program that enables the user to freely combine several orthogonal aspects of search, resulting in a search engine tailored to the user's needs. The abstractions developed here support fully automatic recomputation with last alternative optimization. They present a clean interface, making the implementation of new exploration strategies simple. Conservative extensions of the abstractions are presented that support best solution search and parallel search as orthogonal modules. IOzSeF, the Interactive Oz Search Factory, implements these abstractions and is freely available for download. © Springer-Verlag Berlin Heidelberg 2005.

关键词： Computer programming

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ProductiveC: Enabling high productivity in c-family languages 15

ProductiveC: Enabling high productivity in c-family language...

引用

12th ACM International Conference on Computing Frontiers, CF 2015

作者： Rong, Hongbo Programming Systems Lab Intel United States

ISBN: (纸本)9781450333580

Today's big data challenge presses for a breakthrough in programming models. A simple programming model capable of both high productivity and high performance is desired. This paper proposes a simple solution to realize a set of restricted yet fundamental productivity features in C-family languages, without sacrificing their efficiency. This is achieved by leveraging a productivity language runtime and compiler analyses. Programmers write a program in the familiar C/C++/ObjectiveC style, without even knowing it is a mix of productivity and efficiency code. The program evolves as both a rapid prototype and efficiency code.

关键词： Productivity

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Parallel programming environment: A key to translating tera-scale platforms into a big success 07

Parallel programming environment: A key to translating tera-...

引用

2007 ACM SIGPLAN Symposium on Principles and Practice of Parallel programming, PPoPP'07

作者： Fang, Jesse Z. Programming Systems Lab. Intel Corporation

ISBN: (纸本)1595936025

Moore's Law will continue to increase the number of transistors on die for a couple of decades, as silicon technology moves from 65nm today to 45nm, 32 nm and 22nm in the future. Since power and thermal constraints increase with frequency, multi-core or many-core microprocessors will be the way of the future. In the near future, hardware platforms will have sixteen or more cores on die to achieve more than one Tera Instructions Per second (TIPs) computation power. These cores will communicate each other through an on-die interconnect fabric with more than one TB/s on-die bandwidth and less than 30 cycles latency. Off-die D-cache will employ 3D stacked memory technology to tremendously increase off-die cache/memory bandwidth and reduce the latency. Fast copper flex cables will link CPU-DRAM on socket and optical silicon photonics will provide up to one Tb/s I/O bandwidth between boxes. The hardware system with TIPs of compute power operating on terabytes of data make this a ?tera-scale? platform. What are the software implications with the hardware changes from uniprocessor to tera-scale platform with many cores as "the way of the future?" It will be a great challenge for programming environments to help programmers develop concurrent code for most client software. A good concurrent programming environment should extend existing programming languages that typical programmers are familiar with, and bring benefits for concurrent programming. There are many research topics. Examples topics include flexible parallel programming models based on needs from applications, better synchronization mechanisms such as Transactional Memory to replace simple ?Thread + Lock? structure, nested data parallel language primitives with new protocols, fine-grained synchronization mechanisms with hardware support, maybe fine-grained message passing, advanced compiler optimizations for the threaded code, and software tools in the concurrent programming environment. A more interesting proble

关键词： Parallel programming

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Domain dependent semantic requirement engineering: Research-in-progress

Domain dependent semantic requirement engineering: Research-...

引用

International Workshop on Domain Engineering, DE@CAiSE 2010 - In Conjunction with the 22nd International Conference on Advanced Information systems Engineering, CAISE 2010

作者： Fischer, Wolf Bauer, Bernhard Programming Distributed Systems Lab University of Augsburg Germany

Requirements Engineering is one of the most important phases in any product development life cycle since it is the basis for the complete software or product design and realization. Therefore in a worst case scenario any error within a requirement can result in a project loss. Computer support for requirement engineers is still premature as most RE applications can not cope with more sophisticated techniques like semantics, natural language processing etc. In this paper we will present the ongoing research work in semantic requirement engineering which will try to close the gap between computer understandable semantics, namely ontologies, and the natural language input of a human.

关键词： Semantics

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Transactional memory introduction 18

Transactional memory introduction

引用

18th IEEE Hot Chips Symposium, HCS 2006

作者： Adl-Tabatabai, Ali-Reza Programming Systems Lab Intel Corporation United States

This article consists of a collection of slides from the author's conference presentation on transactional memory (TM). Some of the specific topics discussed include: an introduction to TM;TM implementation techni...

ISBN: (纸本)9781467388672

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Software transactional memory 18

Software transactional memory

引用

18th IEEE Hot Chips Symposium, HCS 2006

作者： Saha, Bratin Programming Systems Lab Intel Corporation United States

ISBN: (纸本)9781467388672

This article consists of a collection of slides from the author's conference presentation on software transactional memory (STM). Some of the specific topics discussed include: how to translate a language construct via STM, including runtime and compiler support;example of hybrid TM;and the outlook for the future development STM and the applications to be supported. © 2006 IEEE.

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