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AccelDroid: Co-designed Acceleration of Android Bytecode

AccelDroid: Co-designed Acceleration of Android Bytecode

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11th IEEE/ACM International Symposium on Code Generation and Optimization (CGO)

作者： Wang, Cheng Wu, Youfeng Cintra, Marcelo Programming Systems Lab Microprocessor and Programming Research Intel Labs

ISBN: (纸本)9781467355254;9781467355247

A hardware/software co-designed processor transparently supports a ubiquitous ISA (e.g. x86) with diversified and innovative microarchitectural implementations. It leverages co-designed HW features and dynamic binary translation (DBT) SW to morph existing binary programs to scale performance and save power. On such systems, the portable bytecode of modern dynamic languages (e.g. Java, JavaScript, etc.) is first translated into the code in the architecture ISA by the just-in-time (JIT) compilation in the bytecode virtual machine, and then into the code in the internal implementation ISA by the DBT. This not only incurs the translation overheads twice, but also brings significant emulation inefficiency as the DBT does not have the high level bytecode information. In this paper, we present AccelDroid, which accelerates the Android Dalvik bytecode execution on the HW/SW co-designed processor through direct bytecode translation in the DBT. Our experiments on a HW/SW co-designed Transmeta Efficeon machine show that AccelDroid can improve performance by 78% and save energy by 40% for the CaffeineMark 3.0 benchmark suite.

关键词： Linux hardware-software codesign instruction sets program compilers virtual machines

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Impacts of multiprocessor configurations on workloads in bioinformatics

Impacts of multiprocessor configurations on workloads in bio...

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19th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD

作者： Wu, Youfeng Breternitz Jr., Mauricio Ying, Victor Programming Systems Lab. Microprocessor Technology Labs. Intel Corporation

ISBN: (纸本)9780769530147

Bioinformatics is among the most active research areas in computer science. In this study, we investigate a suite of workloads in bioinformatics on two multiprocessor systems with different configurations, and examine the effects of the configurations on the performance of the workloads. Our result indicates that the configurations of the multiprocessor systems have significant impact on the performance and scalability of the workloads. For example, a number of workloads have significantly higher scalability on one of the systems, but poorer absolute performance than on the other system. However, traditional scalability failed to capture the impacts of the system configurations on the workloads. We present insights on what kinds of workloads will run faster on which systems and propose new metrics to capture the impacts of multiple processor configurations on the workloads. These findings not only provide an easy way to compare results running on different systems, but also enable re-configuration of the underlying systems to run specific workloads efficiently. We also show how processor mapping and loop spreading may help map the workoads to the underlining multiprocessor configuration and achieve consistent scalability for these workloads. © 2007 IEEE.

关键词： Bioinformatics

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From locks to correct and efficient transactional memory

From locks to correct and efficient transactional memory

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作者： Wang, Cheng Wu, Youfeng Programming Systems Lab Microprocessor and Programming Research Intel Labs 2200 Mission College Blvd. Santa Clara CA 95052 United States

Transactional memory addresses a number of important issues in lock-based parallel programs. Unfortunately, the semantics of transactions are different from those of critical sections defined by locks. The semantic differences make it difficult to correctly port existing lock-based programs to transaction-based programs. Experienced programmers accustomed to lock-based programming can easily make mistakes in transaction-based programming as parallel programs running correctly using locks can run incorrectly when critical sections are converted to using transactions. This problem becomes even more severe in porting lock-based programs to use the efficient software transactional memory. In this paper, we first identify three necessary properties in a program for the program execution using transactions to be equivalent to the program execution using locks. Assuming that the input lock-based program satisfies the necessary properties (i.e., a well-behaved parallel program), we next present a correctness condition to verify the transactional memory implementation in order for the program execution using transactions to be equivalent to the program execution using locks. Finally, we develop a correct and efficient software transactional memory implementation that satisfies the correctness condition so that locks in the well-behaved parallel programs can be converted to use the efficient software transactional memory easily and correctly. © 2012 World Scientific Publishing Company.

关键词： Locks (fasteners)

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From lock to correct and efficient software transactional memory

From lock to correct and efficient software transactional me...

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2010 Workshop on Interaction between Compilers and Computer Architecture, INTERACT-14

作者： Wang, Cheng Wu, Youfeng Programming Systems Lab. Microprocessor and Programming Research Intel Labs. 2200 Mission College Blvd Santa Clara CA 95053 United States

ISBN: (纸本)9781605589213

Transactional memory solves many problems in lock-based parallel programs. Unfortunately, the semantics of transactions are different from those of critical sections defined by locks. The semantic differences make it difficult to correctly port existing lock-based programs to transaction-based programs. Experienced programmers accustomed to lock-based programming can easily make mistakes in transaction-based programming as parallel programs running correctly using locks can run incorrectly when converted to using transactions. This problem becomes even more severe in the efficient software transactional memory implementing weak isolation, optimistic read concurrency management and eager version management. In this paper, we first identify three necessary properties in a program for the program execution using transactions to be equivalent to the program execution using locks. Assuming that the input lock-based program satisfies the necessary properties (i.e. well-behaved parallel programs), we next present a correctness condition for the program execution using transactions to be equivalent to the program execution using locks. Finally, we develop a correct and efficient software transactional memory implementation that satisfies the correctness condition so that locks in the well behaved parallel programs can be converted to use efficient software transactional memory easily and correctly. Copyright © 2010 ACM.

关键词： Locks (fasteners)

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Modeling and performance evaluation of TSO-preserving binary optimization

Modeling and performance evaluation of TSO-preserving binary...

引用

20th International Conference on Parallel Architectures and Compilation Techniques, PACT 2011

作者： Wang, Cheng Wu, Youfeng Programming Systems Lab. Microprocessor and Programming Research Intel Labs. 2200 Mission College Blvd. Santa Clara CA 95052 United States

ISBN: (纸本)9780769545660

Program optimization on multi-core systems must preserve the program memory consistency. This paper studies TSO-preserving binary optimization. We introduce a novel approach to formally model TSO-preserving binary optimization based on the formal TSO memory model. The major contribution of the modeling is a sound and complete algorithm to verify TSO-preserving binary optimization with O(N2) complexity. We also developed a dynamic binary optimization system to evaluate the performance impact of TSO-preserving optimization. We show in our experiments that, dynamic binary optimization without memory optimizations can improve performance by 8.1%. TSOpreserving optimizations can further improve the performance by 4.8% to a total 12.9%. Without considering the restriction for TSO-preserving optimizations, the dynamic binary optimization can improve the overall performance to 20.4%. © 2011 IEEE.

关键词： Binary Optimization Heuristic algorithms Instruction sets Load modeling Memory management Optimization TSO-preserving binary optimization TSO-preserving optimization Total Store Ordering dynamic binary optimization formal TSO memory model multicore system

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Modeling and Performance Evaluation of TSO-Preserving Binary Optimization

Modeling and Performance Evaluation of TSO-Preserving Binary...

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International Conference on Parallel Architecture and Compilation Techniques (PACT)

作者： Cheng Wang Youfeng Wu Programming Systems Lab Microprocessor and Programming Research INTEL Research Laboratory Santa Clara CA USA

Program optimization on multi-core systems must preserve the program memory consistency. This paper studies TSO-preserving binary optimization. We introduce a novel approach to formally model TSO-preserving binary optimization based on the formal TSO memory model. The major contribution of the modeling is a sound and complete algorithm to verify TSO-preserving binary optimization with O(N 2 ) complexity. We also developed a dynamic binary optimization system to evaluate the performance impact of TSO-preserving optimization. We show in our experiments that, dynamic binary optimization without memory optimizations can improve performance by 8.1%. TSO-preserving optimizations can further improve the performance by 4.8% to a total 12.9%. Without considering the restriction for TSO-preserving optimizations, the dynamic binary optimization can improve the overall performance to 20.4%.

关键词： Optimization Instruction sets Load modeling Memory management Heuristic algorithms

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Enhanced code density of embedded CISC processors with Echo technology 05

Enhanced code density of embedded CISC processors with Echo ...

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3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and systems Synthesis CODES+ISSS 2005

作者： Wu, Youfeng Breternitz Jr., Mauricio Hum, Herbert Peri, Ramesh Pickett, Jay Programming Systems Lab. Intel Labs. 2200 Mission College Blvd Santa Clara CA 95054 United States Low Power Microprocessor Lab. Intel Labs. 2200 Mission College Blvd Santa Clara CA 95054 United States Compiler Lab. Intel Labs. 2200 Mission College Blvd Santa Clara CA 95054 United States

ISBN: (纸本)1595931619

Code density is an important issue in memory constrained systems. Some RISC processor, e.g. the THUMB extension in the ARM processor, supports aggressive code size reduction even at the cost of significant performance loss. In this paper, we develop an algorithm that utilizes a set of novel variable length Echo instructions and evaluate its effectiveness for IA32 binaries. Our experiments show that IA32 processor equipped with Echo instructions is capable of achieving a similar code density as the THUMB extension in the ARM instruction set with significantly lower performance penalty. Copyright 2005 ACM.

关键词： microprocessor chips

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