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International Symposium on Code Generation and Optimization (CGO)

作者： Youfeng Wu Shiliang Hu Edson Borin Cheng Wang Programming Systems Laboratory INTEL Research Laboratory Santa Clara CA USA Institute of Computing State University of Campinas-UNICAMP Campinas Brazil

ISBN: (纸本)9781612843568

It is increasingly challenging to improve single thread performance because power/energy consumption becomes a major barrier to achieve significantly higher performance for general purpose cores. General purpose processors are designed to perform well in a wide variety of market segments, at the cost of having significantly lower performance-per-watt than special purpose processors targeting limited applications or market segments. In this paper, we propose a HW/SW co-designed heterogeneous multi-core virtual machine, called TwinPeaks, which integrates a set of less general but power efficient cores and uses dynamic binary optimization to schedule code regions to run on the most efficient cores. Our experiment and analysis indicate that TwinPeaks with a wide in-order core and a narrow out-of-order core may achieve 108% performance at ~71% energy of a big 4-wide out-of-order core.

关键词： Switches Multicore processing Virtual machining Optimization Out of order Energy consumption

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12-OR

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Human Immunology 2012年 73卷 10-10页

作者： Melinda V. Rastrou Cherie L. Holcomb Tim C. Williams Damian Goodridge Ana M. Lazaro Marcel Tilanus Henry A. Erlich Research Human Genetics Roche Molecular Systems Inc. Pleasanton CA USA Research Children’s Hospital and Research Center Oakland CA USA Programming Conexio Genomics Perth Australia C. W. Bill Young/Department of Defense Georgetown University Washington DC USA Transplantation Immunology Tissue Typing Laboratory Maastricht University Medical Center Maastricht Netherlands

Aim Genotyping of DRB1 and DRB3/4/5 is performed in our lab using generic DRB PCR primers, followed by sequencing on the 454 GS FLX and use of Conexio Genomics software. During genotyping homozygous cell lines, we detected additional sequences at about 7% of the read depth of the reported true allele. These artifacts appeared to be PCR crossovers between the DRB1 and DRB3/4/5 sequences. The crossovers usually had one or more mismatches with the IMGT database but occasionally matched a very rare allele (e.g. DRB1 ∗ 03:42). We performed a study to determine if these sequences were in vitro artifacts and to determine if some rare DRB alleles in the IMGT database might, in fact, be in vitro artifacts that had been submitted. Methods To test for in vitro artifact formation during late cycles of genomic PCR, we amplified the DRB loci from 21 homozygous cells lines under both our standard PCR conditions (35 cycles) and a reduced number of cycles (28), followed by 454 sequencing. Using the same PCR conditions, we also sequenced the DRB loci of four samples, each of which had previously been identified as having a novel DRB allele that was subsequently submitted to the IMGT database. Results For all homozygous 21 cell lines, amplification for 35 cycles gave low abundance sequences as possible “second alleles.” In 36% of the cases, these artifactual sequences corresponded to named alleles. Such sequences were not detected with amplification for 28 cycles. In the case of 4 samples with rare alleles previously submitted to the IMGT, we found that 3 were true alleles. The fourth, while not a crossover product, contained a sequencing error which was revealed by our 454 HLA genotyping assay. Conclusions Formation of in vitro crossover products of the DRB loci can occur in late cycles of PCR. PCR conditions have been identified that minimize generation of these in vitro artifacts. Clonal sequencing on the 454 GS FLX is a valuable method for revealing both these artifacts and tradit

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Data envelopment analysis for optimal generators start-up strategy

Data envelopment analysis for optimal generators start-up st...

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8th International Conference on Advances in Power System Control, Operation and Management (APSCOM 2009)

作者： Q. Liu L. B. Shi Y. X. Ni L. Zh. Yao M. Bazargan Programming Research Center CPECC China National Key Laboratory of Power Systems in Shenzhen Tsinghua University China Technology Centre AREVA T and D Inc. UK

An optimal strategy involving the corresponding model and approach to the generators start-up during power system restoration is presented. The aim of the method is to maximize the total power generation capability (MWh) over an optimization time period whilst considering the corresponding constraints. The Data Envelopment Analysis (DEA) method is employed to get an effective assessment towards each generator (to be cranked) by the newly introduced indices derived from the objective function together with its constraints. As a result, the relative efficiency of each generator to be started can be evaluated comprehensively and objectively. On the other hand, the priority for each generator start-up can be determined as well. The proposed method, to some extent, can make the trade off between the simulation precision and the computing efforts much better. Case study based on a 12-generator modified real-sized system illustrate that the proposed strategy could provide more comprehensive and objective decision reference.

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Performance Characterization of SPEC CPU2006 Benchmarks on Intel and AMD Platform

Performance Characterization of SPEC CPU2006 Benchmarks on I...

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International Workshop on Education Technology and Computer Science, ETCS

作者： Shengmei Li Buqi Cheng Xingyu Gao Lin Qiao Zhizhong Tang Department of Computer Science and Technology Tsinghua University Beijing China Programming Systems Laboratory Intel China Research Center Limited Beijing China Chinese Academy and Sciences Beijing China

For understanding the performance differences caused by different computer architectures and optimization technologies, the paper characterizes performance of SPEC CPU2006 benchmarks both on Intel and AMD platform. Using the performance events collected by Performance Monitor Unit, we compare their performance differences and analyze the causes from the features of architectures and the optimization technologies. Our results and analysis help the programmers better understand the memory performance and branch prediction performance which are caused by architectures and guide them in the optimization. The analysis also help the processor architects better balance among the key architecture factors such as memory disambiguation and hardware prefetch when doing architecture design decision.

关键词： Microarchitecture Decoding Educational technology Paper technology programming profession Performance analysis Computer science Computer architecture Hardware Prefetching

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Software transactional memory

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Queue 2008年第5期6卷 46-58页

作者： Cascaval, Calin Blundell, Colin Michael, Maged Cain, Harold W. Wu, Peng Chiras, Stefanie Chatterjee, Siddhartha Programming models and tools for scalable systems IBM's T.J. Watson Research Center University of Pennsylvania IBM's Systems and Technology Group Austin Research Laboratory Department of Computer Science University of Texas Austin United States

No abstract available

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Characterization and analysis of HMMER and SVM-RFE parallel bioinformatics applications

Characterization and analysis of HMMER and SVM-RFE parallel ...

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IEEE International Workshop/Symposium on Workload Characterization

作者： U. Srinivasan Peng-Sheng Chen Qian Diao Chu-Cheow Lim E. Li Yongjian Chen R. Ju Yimin Zhang Programming Systems Laboratoryoratory Microprocessor Technology Laboratory Intel Corporation Santa Clara CA USA Architecture Research Laboratoryoratory Microprocessor Technology Laboratory Intel Corporation Santa Clara CA USA

Bioinformatics applications constitute an emerging data-intensive, high-performance computing (HPC) domain. While there is much research on algorithmic improvements, (2004), the actual performance of an application also depends on how well the program maps to the target hardware. This paper presents a performance study of two parallel bioinformatics applications HMMER (sequence alignment) and SVM-RFE (gene expression analysis), on Intel x86 based hyperthread-capable (2002) shared-memory multiprocessor systems. The performance characteristics varied according to the application and target hardware characteristics. For instance, HMMER is compute intensive and showed better scalability on a 3.0 GHz system versus a 2.2 GHz system. However, SVM-RFE is memory intensive and showed better absolute performance on the 2.2 GHz machine which has better memory bandwidth. The performance is also impacted by processor features, e.g. hyperthreading (HT) (2002) and prefetching. With HMMER we could obtain -75% of the performance with HT enabled with respect to doubling the number of CPUs. While load balancing optimizations can provide speedup of -30% for HMMER on a hyperthreading-enabled system, the load balancing has to adapt to the target number of processors and threads. SVM-RFE benefits differently from the same load-balancing and thread scheduling tuning. We conclude that compiler and runtime optimizations play an important role to achieve the best performance for a given bioinformatics algorithm.

关键词： Hidden Markov models Bioinformatics Hardware Load management Yarn Gene expression Performance analysis Multiprocessing systems Scalability Bandwidth

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Performance potentials of compiler-directed data speculation

Performance potentials of compiler-directed data speculation

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IEEE International Symposium on Performance Analysis of systems and Software

作者： Youfeng Wu Li-Ling Chen R. Ju J. Fang Programming Systems Research Laboratory INTEL Research Laboratory Santa Clara CA USA

Compiler-directed data speculation has been implemented on Itanium systems to allow for a compiler to move a load across a store even when the two operations are potentially aliased This not only breaks data dependency to reduce critical path length, but also allows a load to be scheduled far apart from its uses to hide cache miss latencies. However, the effectiveness of data speculation is affected by the sophistication of alias analysis technique as well as the aggressiveness of the instruction scheduler. In general, the more sophisticated is the alias analysis technique, the less performance gain is from data speculation, and the more aggressive is the instruction scheduler, the more opportunity is for data speculation. In this paper we evaluate in various scenarios the performance potentials of data speculation for SPEC2000C benchmarks. For each scenario, we determine the performance contributions of data speculation due to both critical path reduction and cache miss latency reduction. We also show interesting statistics about the effects of scheduling constraints, the percentage of critical dependencies, the impacts of cache miss latencies, and the distances between the load locations before and after data speculation.

关键词： Delay Processor scheduling Performance analysis Educational institutions Performance gain Performance evaluation Statistics Runtime

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Accuracy of profile maintenance in optimizing compilers

Accuracy of profile maintenance in optimizing compilers

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Annual Workshop on Interaction between Compilers and Computer Architectures

作者： Youfeng Wu Programming Systems Research Laboratory Intel Corporation Santa Clara CA USA

ISBN: (纸本)0769515347

Modern processors rely heavily on optimizing compilers to deliver their performance potentials. The compilers, in turn, rely greatly on profile information to focus the optimization efforts and better match the generated code with the target machines. Maintaining the profile in an optimizing compiler is important as many optimizations can benefit from profile information and they are often performed one after the other. Maintaining a profile is, however, tedious and error prone. An erroneous profile is not easy to detect as it affects only the performance, not the correctness, of a program. Maintaining a profile also inherently loses accuracy, as the profile update operations often have to use probabilistic approximation. In this paper, we measure the accuracy of maintaining CFG profiles in a high-performance optimizing compiler. Our data indicates that the compiler maintains the profile more accurately within individual functions than globally across functions, and function inlining may be responsible for the loss of profile accuracy globally. We also identify a number of research issues related to profile maintenance.

关键词： Optimizing compilers Frequency Flow graphs Educational institutions Productivity programming profession Automatic control Conferences Computer architecture

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Implementation lessons of performance prediction tool for parallel conservative simulation 6

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6th International European Conference on Parallel Computing, Euro-Par 2000

作者： Lim, Chu-Cheow Low, Yoke-Hean Gan, Boon-Ping Cai, Wentong Intel Corporation SC12-305 2000 Mission College Blvd Santa ClaraCA95052-8119 United States Programming Research Group Oxford University Computing Laboratory University of Oxford OxfordOX1 3QD United Kingdom Gintic Institute of Manufacturing Technology 71 Nanyang Drive Singapore638075 Singapore Center for Advanced Information Systems School of Applied Science Nanyang Technological University Singapore639798 Singapore

ISBN: (纸本)9783540679561

Performance prediction is useful in helping parallel programmers answer questions such as speedup scalability. Performance prediction for parallel simulation requires first working out the performance analyzer algorithms for specific simulation protocols. In order for the prediction results to be close to the results from actual parallel executions, there are further considerations when implementing the analyzer. These include (a) equivalence of code between the sequential program and parallel program, and (b) system effects (e.g. cache miss rates and synchronization overheads in an actual parallel execution). This paper describes our investigations into these issues on a performance analyzer for a conservative, "super-step" (synchronous) simulation protocol. © Springer-Verlag Berlin Heidelberg 2000.

关键词： Forecasting

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Fast and effective query refinement 97

Fast and effective query refinement

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20th Annual International ACM SIGIR Conference on research and Development in Information Retrieval

作者： Velez, B Weiss, R Sheldon, MA Gifford, DK Programming Systems Research Group MIT Laboratory for Computer Science Lotus Development Corporation

ISBN: (纸本)0897918363

Query Refinement is an essential information retrieval tool that interactively recommends new terms related to a particular query. This paper introduces concept recall, an experimental measure of an algorithm's ability to suggest terms humans have judged to be semantically related to an information need. This study uses precision improvement experiments to measure the ability of an algorithm to produce single term query modifications that predict a user's information need as partially encoded by the query. An oracle algorithm produces ideal query modifications, providing a meaningful context for interpreting precision improvement results. This study also introduces RMAP, a fast and practical query refinement algorithm that refines multiple term queries by dynamically combining precomputed suggestions for single term queries. RMAP achieves accuracy comparable to a much slower algorithm, although both RMAP and the slower algorithm lag behind the best possible term suggestions offered by the oracle. We believe RMAP is fast enough to be integrated into present day Internet search engines: RMAP computes 100 term suggestions for a 160,000 document collection in 15 ms on a low-end PC.

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