Strong C-C bonds,nanoscale cross-section and low atomic number make single-walled carbon nanotubes(SWCNTs)a potential candidate material for integrated circuits(ICs)applied in outer ***,very little work combines the s...
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Strong C-C bonds,nanoscale cross-section and low atomic number make single-walled carbon nanotubes(SWCNTs)a potential candidate material for integrated circuits(ICs)applied in outer ***,very little work combines the simulation calculations with the electrical measurements of SWCNT field-effect transistors(FETs),which limits further understanding on the mechanisms of radiation ***,SWCNT film-based FETs were fabricated to explore the total ionizing dose(TId)anddisplacement damage effect on the electrical performance under low-energy proton irradiation with different fluences up to 1×1015 p/*** negative shift of the threshold voltage and obvious decrease of the on-state current verified the TId effect caused in the oxide *** stability of the subthreshold swing and the off-state current reveals that the displacement damage caused in the CNT layer is not serious,which proves that the CNT film is ***,according to the simulation,we found the displacement damage caused by protons is different in the source/drain contact area and channel area,leading to varying degrees of change for the contact resistance and sheet *** analyzed the simulation results and electrical measurements,we explained the low-energy proton irradiation mechanism of the CNT FETs,which is essential for the construction of radiation-hardened CNT film-based ICs for aircrafts.
SOI devices are of great interest in aerospace applications for their candidate in radiation hardened solutions. Hot carrier effects are investigated in H shaped partially depleted SOI based NMOSFET. We analyze differ...
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ISBN:
(纸本)9781479966332
SOI devices are of great interest in aerospace applications for their candidate in radiation hardened solutions. Hot carrier effects are investigated in H shaped partially depleted SOI based NMOSFET. We analyze different responses fordifferent bias conditions. The experimental results show that the high gate anddrain voltage condition is the worst case for body tied H shaped SOI-NMOS. After 2000 seconds stress in room temperature, the device physical parameters' degradations show clearly different from maximum substrate current stress condition (VG≈=0.5Vd) that is transconductance increasing with the stress time.
作者：
Hayashi, TFukuda, KOhno, MNishi, KKita, AVLSI R&D Center
OKI Electric Industry Company Ltd. Hachioji-shi Japan 193 Graduated from the Science University of Tokyo
Dept. of Applied Physics in 1986 and joined Oki Electric. Since then he has been engaged in research on the reliability of MOS transistors and silicon oxide films. Since 1994 he has been engaged in the development of flash memory. He is a member of the Applied Physics Society. Graduated from the University of Tokyo
Dept. of Applied Physics in 1983 and joined Oki Electric in 1985. Since then he has been engaged in research on the semiconductor process and device simulation. In 1990 he participated in joint research at the Technical University of Aachen. He is a member of the Applied Physics Society. Graduated from the Tokyo University of Agriculture and Technology
Dept. of Electrical Engineering in 1980 and completed an MS course in 1983. In 1986 he completed the doctoral course at Shizuoka University. He then joined Oki Electric where he has been engaged in research on ULSI processes. He is now a manager responsible for flash memory at the VLSI R&D Center. He holds a doctorate in engineering. He is a member of the Applied Physics Society. Graduated from the University of Tokyo
Dept. of Applied Physics in 1973 and joined Oki Electric. He was engaged in the development of integrated circuit logic simulation technology and bipolar process technology and since 1980 he has been engaged in research on process/device simulation and modeling. Presently he is a senior manager at the VLSI R&D Center. In 1982–1984 he was a Visiting Scholar at MIT. He holds a doctorate in engineering. He is a member of the Applied Physics Society and a senior member of IEEE. Graduated from Tokyo Institute of Technology
Dept. of Chemical Engineering in 1978 and completed the MS program in 1930. In that year he joined Oki Electric. Since then he has been engaged in CMOS process design for DRAM and flash memory. He is now a manager at the VLSI R&D Center. He is a member of the Applied Physics Society.
In order to analyze the BBT (band-to-band tunneling) phenomenon in flash memory cells by simulation, a new model is proposed, which improves on the BBT model by introducing the concept of ''average electric fi...
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In order to analyze the BBT (band-to-band tunneling) phenomenon in flash memory cells by simulation, a new model is proposed, which improves on the BBT model by introducing the concept of ''average electric field.'' This model agrees well with the measuredresults in a wide drain N-concentration range. Using this model, the reliability of memory cells is analyzed. It is found that the difference of the amount of BBT generation does not directly affect the endurance characteristics but does affect the disturb characteristics. The same model can be used to analyze problem points of the present cells and to estimate the BBT current of next-generation devices accurately.
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