A novel amorphous silicon driving circuitry, operated in Capacitively Coupleddriving (CCd) method, is proposed and analyzed. By employing the circuitry for TFT-LCd gate and storage capacitor lines, line inversion dri...
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A novel amorphous silicon driving circuitry, operated in Capacitively Coupleddriving (CCd) method, is proposed and analyzed. By employing the circuitry for TFT-LCd gate and storage capacitor lines, line inversion driving mode can be realized with dC voltage on common electrode. With dC voltage on color filter common electrode, a capacitive touch panel is no longer suffered from driving pulse cross-talk in a conventional line inversion TFT-LCd. � 2009 SId.
Electronic structure calculations are employed in order to investigate the cohesive properties (lattice parameter, enthalpy of formation, and bulk modulus) of random Fe-Cr alloys as a function of composition and magne...
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Electronic structure calculations are employed in order to investigate the cohesive properties (lattice parameter, enthalpy of formation, and bulk modulus) of random Fe-Cr alloys as a function of composition and magnetic state, as well as to derive the chemical and magnetic exchange interactions of the constituent atoms. The calculations predict certain anomalies in the cohesive properties of ferromagnetic alloys at a concentration of about 7 at % Cr; these anomalies may be related to the changes in Fermi-surface topology that occur with composition in this alloy system. The obtained interatomic interactions are used as parameters in the configurational (Ising) and magnetic (Heisenberg) Hamiltonians for modeling finite-temperature thermodynamic properties of the alloys. We discuss the approximations and limitations of similar modeling approaches, investigate the origin of existing difficulties, and analyze possible ways of extending the theoretical models in order to capture the essential physics of interatomic interactions in the Fe-Cr or similar alloys where magnetism plays a crucial role in the phase stability.
Negative bias temperature instability (NBTI) strongly limits reliability of PMOS devices by degradation of threshold voltage, subthreshold slope and transconductance. The physical understanding of the NBTI mechanism i...
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Negative bias temperature instability (NBTI) strongly limits reliability of PMOS devices by degradation of threshold voltage, subthreshold slope and transconductance. The physical understanding of the NBTI mechanism is essential for searching paths of NBTI alleviation and providing realistic predictions for CMOS reliability. This work presents a new NBTI model based on hole trapping/detrapping accompanied by structural relaxation in the host dielectric. Simulations account for a time and T dependence of the drain current degradation during NBTI stress. dynamic NBTI effects are then explained by alternative hole capture and emission during stress andrelaxation stages. The impact of the activation energy dispersion on relaxation times is finally discussed.
Hot carrier (HC) reliability of gate-all-around twin Si nanowire field effect transistor (GAA TSNWFET) is reported anddiscussed with respect to size and shape of nanowire channel, gate length, thickness and kind of g...
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Hot carrier (HC) reliability of gate-all-around twin Si nanowire field effect transistor (GAA TSNWFET) is reported anddiscussed with respect to size and shape of nanowire channel, gate length, thickness and kind of gate dielectric in detail. Smaller nanowire channel size, shorter gate length and thinner gate oxide down to 2 nm thickness show worse hot carrierreliability. The worst V d for 10 years guaranty, 1.31 V, satisfies requirement of ITrS roadmap.
The phase-change memory (PCM) technologyrepresents one of the most attractive concepts for next generation data storage. PCM behavior is mainly limited by the structural relaxation (Sr) and by the crystallization of ...
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The phase-change memory (PCM) technologyrepresents one of the most attractive concepts for next generation data storage. PCM behavior is mainly limited by the structural relaxation (Sr) and by the crystallization of an amorphous chalcogenide material: the ternary alloy Ge 2 Sb 2 Te 5 . Sr is a local structural-rearrangement at the atomic/bonding scale and crystallization is the reaching of a periodic atomic structure. While the retention capabilities related to crystallization have been already extensively addressed in the literature, both at the single-cell and at the statistical level, those related to Sr have been mainly studied at the intrinsic level and a statistical analysis at the device level is still lacking. The purpose of this paper is to study the statistical and scaling behavior of the Sr phenomenon in PCM devices, through experimental and modeling tools, allowing for long term, physics-based, reliability extrapolations in large-scaled PCM arrays.
This work investigates for the first time charge-granularity effects during channel hot-electron programming of NOr flash memories, comparing the granular electron injection and the random telegraph noise limitations ...
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This work investigates for the first time charge-granularity effects during channel hot-electron programming of NOr flash memories, comparing the granular electron injection and the random telegraph noise limitations to the accuracy of the programming algorithm. The spread of the threshold voltage shift that is determined by the electron injection statistics is studied as a function of the channel hot-electron programming conditions, explaining the results by an analytical model accounting for the sub-Poissonian nature of the electron transfer to the floating gate. The scaling trend of the injection statistical spread is then investigated on NOr technologies ranging from 180 to 45 nm and its contribution to the width of the threshold voltage distribution in presence of a program verify level is separated from that given by random telegraph noise.
Fine patterning technologies - e-beam lithography, SPT (spacer patterning technology) and SadPT (self aligneddouble patterning technology)-have been introduced to develop a single unit of nano-scale MOSFET. However, ...
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Fine patterning technologies - e-beam lithography, SPT (spacer patterning technology) and SadPT (self aligneddouble patterning technology)-have been introduced to develop a single unit of nano-scale MOSFET. However, in order to achieve manufacturable high density NANd Flash memories, the merits anddemerits of each technology should be considered in three points of view: device characteristics, process controllability and mass production. In this paper, we suggest the appropriate technology for particular cell types, CTF (charge trap flash) cell, floating poly-Si gate cell, and for process steps such as active, gate and bit-line.
This paper presents an estimation method of rotational direction and speed for free running AC machines driven by an inverter without speed and voltage sensor. The method has four estimation modes, and the method util...
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This paper presents an estimation method of rotational direction and speed for free running AC machines driven by an inverter without speed and voltage sensor. The method has four estimation modes, and the method utilized only the measured phase current of machines. The amplitude of current during the estimation is suppressed to lower levels such as the exciting current, which is smaller than the rated value. Good performance of this method is confirmed by the experiment.
Vertical NANd flash memory cell array by TCAT (terabit cell array transistor) technology is proposed. damascened metal gate SONOS type cell in the vertical NANd flash string is realized by a unique dasiagate replaceme...
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Vertical NANd flash memory cell array by TCAT (terabit cell array transistor) technology is proposed. damascened metal gate SONOS type cell in the vertical NANd flash string is realized by a unique dasiagate replacementpsila process. Also, conventional bulk erase operation of the cell is successfully demonstrated. All advantages of TCAT flash is achieved without any sacrifice of bit cost scalability.
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